ARM: mmp: Use M2 instead of D1P for PXA988

There is a known silicon issue which will cause D1P's power is even higher
than M2 on Zx. Remove D1P support to use M2 instead.

This issue will be fixed on A0. Remember to add D1P support back then.

JIRA index: EMEI-101

Change-Id: Iee664626debc3ae9dd2f91c5d9a8a9af75db57ff
Signed-off-by: Raul Xiong <xjian@marvell.com>

1 files changed, 9 insertions, 23 deletions

diff --git a/arch/arm/mach-mmp/pxa988_lowpower.c b/arch/arm/mach-mmp/pxa988_lowpower.c
index 091034e8746e07..b7c832654c16ce 100644
--- a/arch/arm/mach-mmp/pxa988_lowpower.c
+++ b/arch/arm/mach-mmp/pxa988_lowpower.c
@@ -222,14 +222,12 @@ back:
 static void pxa988_lowpower_config(u32 cpu,
 			u32 power_state, u32 lowpower_enable)
 {
-	u32 core_idle_cfg, mp_idle_cfg, apcr, mc_slp_type, apmu_debug;
+	u32 core_idle_cfg, mp_idle_cfg, apcr;
 
 	pmu_register_lock();
 	core_idle_cfg = __raw_readl(APMU_CORE_IDLE_CFG[cpu]);
 	mp_idle_cfg = __raw_readl(APMU_MP_IDLE_CFG[cpu]);
 	apcr = __raw_readl(MPMU_APCR);
-	mc_slp_type = __raw_readl(APMU_MC_HW_SLP_TYPE);
-	apmu_debug = __raw_readl(APMU_DEBUG);
 
 	if (lowpower_enable) {
 		switch (power_state) {
@@ -247,19 +245,17 @@ static void pxa988_lowpower_config(u32 cpu,
 			/* fall through */
 		case POWER_MODE_APPS_SLEEP:
 			apcr |= PMUM_SLPEN;
+			apcr |= PMUM_AXISD;
+			apcr |= PMUM_DDRCORSD;
 			/* fall through */
 		case POWER_MODE_APPS_IDLE:
-			/*
-			 * FIXME: This is for PXA988 Z0, for A0 here we only
-			 * need to vote PMUM_AXISD.
-			 * Note that on Z0 we have to modify APMU_MC_HW_SLP_TYPE
-			 * to change ddr sleep type from self-refresh to 0x4, a
-			 * reserved value. This makes ddr accessable in AP_IDLE.
-			 * Also we need to set APMU_DEBUG register to make it
-			 * enter AP_IDLE. This is supposed to be fixed on A0.
+			/* FIXME:
+			 * There is a known silicon issue which will cause D1P's
+			 * power is even higher than M2 on Zx. So use M2 instead
+			 * of D1P on Zx.
+			 * This issue will be fixed on A0.
+			 * JIRA index: EMEI-101
 			 */
-			apcr |= PMUM_AXISD;
-			apcr |= PMUM_DDRCORSD;
 			/* fall through */
 		case POWER_MODE_CORE_POWERDOWN:
 			core_idle_cfg |= PMUA_CORE_POWER_DOWN;
@@ -286,12 +282,6 @@ static void pxa988_lowpower_config(u32 cpu,
 		default:
 			WARN(1, "Invalid power state!\n");
 		}
-
-		if (power_state == POWER_MODE_APPS_IDLE) {
-			mc_slp_type &= ~0x7;
-			mc_slp_type |= 0x4;
-			apmu_debug |= (1 << 14) | (1 << 23);
-		}
 	} else {
 		core_idle_cfg &= ~(PMUA_CORE_IDLE | PMUA_CORE_POWER_DOWN |
 				PMUA_CORE_L1_SRAM_POWER_DOWN);
@@ -301,8 +291,6 @@ static void pxa988_lowpower_config(u32 cpu,
 				PMUA_MP_MASK_CLK_OFF);
 		apcr &= ~(PMUM_DDRCORSD | PMUM_APBSD | PMUM_AXISD |
 			PMUM_VCTCXOSD | PMUM_STBYEN | PMUM_SLPEN);
-		mc_slp_type &= ~0x7;
-		apmu_debug &= ~((1 << 14) | (1 << 23));
 		/* disable the gpio edge for cpu active states */
 		mmp_gpio_edge_disable();
 	}
@@ -319,8 +307,6 @@ static void pxa988_lowpower_config(u32 cpu,
 	__raw_writel(core_idle_cfg, APMU_CORE_IDLE_CFG[cpu]);
 	__raw_writel(mp_idle_cfg, APMU_MP_IDLE_CFG[cpu]);
 	__raw_writel(apcr, MPMU_APCR);
-	__raw_writel(mc_slp_type, APMU_MC_HW_SLP_TYPE);
-	__raw_writel(apmu_debug, APMU_DEBUG);
 	pmu_register_unlock();
 }