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authorMoran Raviv <moranr@marvell.com>2012-07-15 13:37:02 +0300
committerLubomir Rintel <lkundrak@v3.sk>2019-07-22 19:39:59 +0200
commit1cccc9340b6b517f098068783d9621a274758ecd (patch)
tree6bb64334a79c040fae49698b4bc482dcd9e16e4c
parent90d58294022bd9692bd341fd94db1cf0c398c325 (diff)
downloadlinux-mmp3-dell-ariel-1cccc9340b6b517f098068783d9621a274758ecd.tar.gz
ARM: pxa978: set HF DDR to 800MTPS
When COMM side request HF DDR, disable PP1,2,3 so PP will be PP4 and up, to allow DDR=800MTPS. This is according to PP table 5.1 Change-Id: I5a422e1a3b8763d1912a1850cd85295d642f2212 Signed-off-by: Moran Raviv <moranr@marvell.com>
-rw-r--r--drivers/char/pxa9xx_acipc.c44
1 files changed, 22 insertions, 22 deletions
diff --git a/drivers/char/pxa9xx_acipc.c b/drivers/char/pxa9xx_acipc.c
index 4686c4a03c7218..84fae050086f7b 100644
--- a/drivers/char/pxa9xx_acipc.c
+++ b/drivers/char/pxa9xx_acipc.c
@@ -484,17 +484,18 @@ struct work_struct acipc_ddr_hi_freq_acquire, acipc_ddr_hi_freq_release;
static void acipc_ddr_hi_freq_acquire_handler(struct work_struct *work)
{
unsigned long flags;
- if (cpu_is_pxa95x()) {
- dvfm_enable_op_name("156M_HF", \
- acipc_lock.dev_idx);
- /* 208MHz and 208+HF should be
- reconsidered by System eng */
- /*dvfm_enable_op_name("208M_HF",\
- acipc_lock.dev_idx);*/
- /*dvfm_disable_op_name("208M", \
- acipc_lock.dev_idx);*/
- }
- dvfm_disable_op_name("156M", acipc_lock.dev_idx);
+
+ if (cpu_is_pxa955() || cpu_is_pxa968()) {
+ dvfm_enable_op_name("156M_HF", acipc_lock.dev_idx);
+ dvfm_disable_op_name("156M", acipc_lock.dev_idx);
+ } else if (cpu_is_pxa978()) {
+ /* allowing 728M and up for DDR = 800MTPS */
+ dvfm_disable_op_name("416M", acipc_lock.dev_idx);
+ dvfm_disable_op_name("312M", acipc_lock.dev_idx);
+ dvfm_disable_op_name("156M", acipc_lock.dev_idx);
+ } else
+ BUG_ON(1);
+
/* MIPSRAM and ACIPC event should be atomic*/
local_irq_save(flags);
acipc_event_set(ACIPC_DDR_260_READY_ACK);
@@ -510,17 +511,16 @@ static void acipc_ddr_hi_freq_acquire_handler(struct work_struct *work)
static void acipc_ddr_hi_freq_release_handler(struct work_struct *work)
{
- dvfm_enable_op_name("156M", acipc_lock.dev_idx);
- if (cpu_is_pxa95x()) {
- /* 208MHz and 208+HF should be
- reconsidered by System eng */
- /*dvfm_enable_op_name("208M", \
- acipc_lock.dev_idx);
- dvfm_disable_op_name("208M_HF", \
- acipc_lock.dev_idx);*/
- dvfm_disable_op_name("156M_HF", \
- acipc_lock.dev_idx);
- }
+ if (cpu_is_pxa955() || cpu_is_pxa968()) {
+ dvfm_enable_op_name("156M", acipc_lock.dev_idx);
+ dvfm_disable_op_name("156M_HF", acipc_lock.dev_idx);
+ } else if (cpu_is_pxa978()) {
+ dvfm_enable_op_name("156M", acipc_lock.dev_idx);
+ dvfm_enable_op_name("312M", acipc_lock.dev_idx);
+ dvfm_enable_op_name("416M", acipc_lock.dev_idx);
+ } else
+ BUG_ON(1);
+
MIPS_RAM_ADD_PM_TRACE(ACIPC_HF_DDR_REL_HANDHELD_MIPS_RAM);
}