must specify sr register (3-bit field) when using fic

2 files changed, 3 insertions, 3 deletions

diff --git a/ipl/crt0.S b/ipl/crt0.S
index d0062db..05c5fc1 100644
--- a/ipl/crt0.S
+++ b/ipl/crt0.S
@@ -159,7 +159,7 @@ mmloop1:
 	ldo		-1(%arg2), %arg2
 	stb		%r19, 0(%arg0)
 	fdc		0(%arg0)
-	fic		0(%arg0)
+	fic		0(%sr0,%arg0)
 	ldo		1(%arg0), %arg0
 	cmpib,<>	-1, %arg2, mmloop1
 	nop
@@ -175,7 +175,7 @@ mmloop2:
 	ldo		-1(%arg2), %arg2
 	stb		%r19, 0(%arg0)
 	fdc		0(%arg0)
-	fic		0(%arg0)
+	fic		0(%sr0,%arg0)
 	ldo		-1(%arg0), %arg0
 	cmpib,<>	-1, %arg2, mmloop2
 	nop
diff --git a/ipl/ipl.c b/ipl/ipl.c
index 71975c5..86803cd 100644
--- a/ipl/ipl.c
+++ b/ipl/ipl.c
@@ -27,7 +27,7 @@ void flush_data_cache(char *start, size_t length)
     do
     {
 	asm volatile("fdc 0(%0)" : : "r" (start));
-	asm volatile("fic 0(%0)" : : "r" (start));
+	asm volatile("fic 0(%%sr0,%0)" : : "r" (start));
 	start += 16;
     } while (start < end);
     asm volatile("fdc 0(%0)" : : "r" (end));