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| author | Biju Das <biju.das@bp.renesas.com> | 2018-07-27 17:27:14 +0100 |
|---|---|---|
| committer | Ben Hutchings <ben.hutchings@codethink.co.uk> | 2018-08-24 19:18:30 +0100 |
| commit | c70a983ef0bb0c936c71d4b5cc23dd173aadcef0 (patch) | |
| tree | 3d894a58505684550d7fea576d07e9d713e4084d | |
| parent | 8614cbbe891d98aa56b8f6d23d28093257e5f039 (diff) | |
| download | linux-cip-c70a983ef0bb0c936c71d4b5cc23dd173aadcef0.tar.gz | |
ARM: dts: r8a7745: Add VSP support
Add VSP support to SoC DT.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Chris Paterson <chris.paterson2@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
(cherry picked from commit 76a2577d97f0b221245e56a17a70bb10a3a97419)
(dropped resets property. changed clocks and power-domains properties.
added vsp device configuration)
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Ben Hutchings <ben.hutchings@codethink.co.uk>
| -rw-r--r-- | arch/arm/boot/dts/r8a7745.dtsi | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index 5cafc30605b315..023d69c2f86936 100644 --- a/arch/arm/boot/dts/r8a7745.dtsi +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -1071,6 +1071,34 @@ status = "disabled"; }; + vsp@fe928000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe928000 0 0x8000>; + interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7745_CLK_VSP1_SY>; + power-domains = <&cpg_clocks>; + + renesas,has-lut; + renesas,has-sru; + renesas,#rpf = <5>; + renesas,#uds = <1>; + renesas,#wpf = <4>; + }; + + vsp@fe930000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe930000 0 0x8000>; + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7745_CLK_VSP1DU0>; + power-domains = <&cpg_clocks>; + + renesas,has-lif; + renesas,has-lut; + renesas,#rpf = <4>; + renesas,#uds = <1>; + renesas,#wpf = <1>; + }; + du: display@feb00000 { compatible = "renesas,du-r8a7745"; reg = <0 0xfeb00000 0 0x40000>; |