diff options
| author | Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> | 2018-07-26 18:42:55 +0100 |
|---|---|---|
| committer | Ben Hutchings <ben.hutchings@codethink.co.uk> | 2018-08-24 19:18:27 +0100 |
| commit | 9edffef988339e88198d9905d58698e230563122 (patch) | |
| tree | 90147dd690dde2a9ec1195b56b9af36b7d69414c | |
| parent | 84e6938b46176a6754b93b36606b460fe01cd715 (diff) | |
| download | linux-cip-9edffef988339e88198d9905d58698e230563122.tar.gz | |
ARM: dts: r8a7745: initial SoC device tree
The initial R8A7745 SoC device tree including CPU0, GIC, timer, SYSC, RST,
CPG, and the required clock descriptions.
Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
(cherry picked from commit c95360247bdd67d39b55f7e743153efa64e4efe3)
(cherry picked again only to get rst node)
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Ben Hutchings <ben.hutchings@codethink.co.uk>
| -rw-r--r-- | arch/arm/boot/dts/r8a7745.dtsi | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index 2e79205bebef6a..f19aed2f12fbcd 100644 --- a/arch/arm/boot/dts/r8a7745.dtsi +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -214,6 +214,11 @@ cpus = <&cpu0 &cpu1>; }; + rst: reset-controller@e6160000 { + compatible = "renesas,r8a7745-rst"; + reg = <0 0xe6160000 0 0x100>; + }; + irqc: interrupt-controller@e61c0000 { compatible = "renesas,irqc-r8a7745", "renesas,irqc"; #interrupt-cells = <2>; |