diff options
| author | Cyril Chemparathy <cyril@ti.com> | 2012-07-16 17:20:17 -0400 |
|---|---|---|
| committer | Cyril Chemparathy <cyril@ti.com> | 2012-09-21 10:43:57 -0400 |
| commit | 964f05f9578dd099563610ebdd9adf30000fa8ed (patch) | |
| tree | 7a4a7dd748661a8ee4e0b66dc76b2400469eea62 | |
| parent | 9fe08194f89e6c23850d0502a4dc0acbc7bc2f89 (diff) | |
| download | linux-keystone-964f05f9578dd099563610ebdd9adf30000fa8ed.tar.gz | |
ARM: LPAE: use 64-bit accessors for TTBR registers
This patch adds TTBR accessor macros, and modifies cpu_get_pgd() and
the LPAE version of cpu_set_reserved_ttbr0() to use these instead.
In the process, we also fix these functions to correctly handle cases
where the physical address lies beyond the 4G limit of 32-bit addressing.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
| -rw-r--r-- | arch/arm/include/asm/proc-fns.h | 24 | ||||
| -rw-r--r-- | arch/arm/mm/context.c | 9 |
2 files changed, 21 insertions, 12 deletions
diff --git a/arch/arm/include/asm/proc-fns.h b/arch/arm/include/asm/proc-fns.h index 75b5f14617c314..2d270b8c6e1aa0 100644 --- a/arch/arm/include/asm/proc-fns.h +++ b/arch/arm/include/asm/proc-fns.h @@ -116,13 +116,27 @@ extern void cpu_resume(void); #define cpu_switch_mm(pgd,mm) cpu_do_switch_mm(virt_to_phys(pgd),mm) #ifdef CONFIG_ARM_LPAE + +#define cpu_get_ttbr(nr) \ + ({ \ + u64 ttbr; \ + __asm__("mrrc p15, " #nr ", %Q0, %R0, c2" \ + : "=r" (ttbr) \ + : : ); \ + ttbr; \ + }) + +#define cpu_set_ttbr(nr, val) \ + do { \ + u64 ttbr = val; \ + __asm__("mcrr p15, " #nr ", %Q0, %R0, c2" \ + : : "r" (ttbr) \ + : "cc"); \ + } while (0) + #define cpu_get_pgd() \ ({ \ - unsigned long pg, pg2; \ - __asm__("mrrc p15, 0, %0, %1, c2" \ - : "=r" (pg), "=r" (pg2) \ - : \ - : "cc"); \ + u64 pg = cpu_get_ttbr(0); \ pg &= ~(PTRS_PER_PGD*sizeof(pgd_t)-1); \ (pgd_t *)phys_to_virt(pg); \ }) diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c index 4e07eec1270dd3..f03437e8035e3c 100644 --- a/arch/arm/mm/context.c +++ b/arch/arm/mm/context.c @@ -16,6 +16,7 @@ #include <asm/mmu_context.h> #include <asm/thread_notify.h> #include <asm/tlbflush.h> +#include <asm/proc-fns.h> static DEFINE_RAW_SPINLOCK(cpu_asid_lock); unsigned int cpu_last_asid = ASID_FIRST_VERSION; @@ -23,17 +24,11 @@ unsigned int cpu_last_asid = ASID_FIRST_VERSION; #ifdef CONFIG_ARM_LPAE void cpu_set_reserved_ttbr0(void) { - unsigned long ttbl = __pa(swapper_pg_dir); - unsigned long ttbh = 0; - /* * Set TTBR0 to swapper_pg_dir which contains only global entries. The * ASID is set to 0. */ - asm volatile( - " mcrr p15, 0, %0, %1, c2 @ set TTBR0\n" - : - : "r" (ttbl), "r" (ttbh)); + cpu_set_ttbr(0, __pa(swapper_pg_dir)); isb(); } #else |