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authorShuai Xue <xueshuai@linux.alibaba.com>2022-08-25 08:33:53 +0800
committerShuai Xue <xueshuai@linux.alibaba.com>2022-08-30 17:11:57 +0800
commit49bded454d33278c1b40a73af04513fefc7da0d6 (patch)
tree91430611f25f1495f229ffe155541afa8f5d54de
parent051c9b4379e3ec45b9f5b52fe73a0acd9343ef42 (diff)
downloadras-tools-49bded454d33278c1b40a73af04513fefc7da0d6.tar.gz
einj_mem_uc: add cases to inject processor error
Signed-off-by: Shuai Xue <xueshuai@linux.alibaba.com>
-rw-r--r--einj_mem_uc.c51
1 files changed, 51 insertions, 0 deletions
diff --git a/einj_mem_uc.c b/einj_mem_uc.c
index 7288eb5..2438110 100644
--- a/einj_mem_uc.c
+++ b/einj_mem_uc.c
@@ -129,6 +129,45 @@ static void inject_uc(unsigned long long addr, void *vaddr, int notrigger)
wfile(EINJ_DOIT, 1);
}
+static void inject_core_ce(unsigned long long addr, void *vaddr, int notrigger)
+{
+ unsigned int cpu;
+
+ PRINT_INJECTING;
+ cpu = sched_getcpu();
+ wfile(EINJ_ETYPE, 0x1);
+ wfile(EINJ_APIC, cpu);
+ wfile(EINJ_FLAGS, 1);
+ wfile(EINJ_NOTRIGGER, notrigger);
+ wfile(EINJ_DOIT, 1);
+}
+
+static void inject_core_non_fatal(unsigned long long addr, void *vaddr, int notrigger)
+{
+ unsigned int cpu;
+
+ PRINT_INJECTING;
+ cpu = sched_getcpu();
+ wfile(EINJ_ETYPE, 0x2);
+ wfile(EINJ_APIC, cpu);
+ wfile(EINJ_FLAGS, 1);
+ wfile(EINJ_NOTRIGGER, notrigger);
+ wfile(EINJ_DOIT, 1);
+}
+
+static void inject_core_fatal(unsigned long long addr, void *vaddr, int notrigger)
+{
+ unsigned int cpu;
+
+ PRINT_INJECTING;
+ cpu = sched_getcpu();
+ wfile(EINJ_ETYPE, 0x4);
+ wfile(EINJ_APIC, cpu);
+ wfile(EINJ_FLAGS, 1);
+ wfile(EINJ_NOTRIGGER, notrigger);
+ wfile(EINJ_DOIT, 1);
+}
+
#ifdef __x86_64__
static void inject_llc(unsigned long long addr, void *vaddr, int notrigger)
{
@@ -663,6 +702,18 @@ struct test {
"mlock", "mlock target page then inject/read to generates SRAR machine check",
mlock_data_alloc, inject_uc, 1, trigger_single, F_MCE|F_CMCI|F_SIGBUS,
},
+ {
+ "core_ce", "Core corrected error",
+ data_alloc, inject_core_ce, 1, trigger_single, F_CMCI,
+ },
+ {
+ "core_non_fatal", "Core deferred error",
+ data_alloc, inject_core_non_fatal, 1, trigger_single, F_CMCI,
+ },
+ {
+ "core_fatal", "Core uncorrected error. Should fatal",
+ data_alloc, inject_core_fatal, 1, trigger_single, F_CMCI|F_FATAL,
+ },
{ NULL }
};