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| author | Shuai Xue <xueshuai@linux.alibaba.com> | 2022-08-20 21:40:15 +0800 |
|---|---|---|
| committer | Shuai Xue <xueshuai@linux.alibaba.com> | 2022-08-30 19:28:21 +0800 |
| commit | 00fac3288314f698d561a95d291b1f5c21bf72ed (patch) | |
| tree | e1e4c07c15e36fc9e996adf3b66f002465aab064 | |
| parent | af0669f8305057bb415b56b02bea70c7cc45fef0 (diff) | |
| download | ras-tools-00fac3288314f698d561a95d291b1f5c21bf72ed.tar.gz | |
einj_mem_uc: add cases for platform specific
Add cases for platform specific, including CMN, GIC, SMMU, etc.
Signed-off-by: Shuai Xue <xueshuai@linux.alibaba.com>
| -rw-r--r-- | einj_mem_uc.c | 122 |
1 files changed, 122 insertions, 0 deletions
diff --git a/einj_mem_uc.c b/einj_mem_uc.c index de0082a..c653a59 100644 --- a/einj_mem_uc.c +++ b/einj_mem_uc.c @@ -197,6 +197,88 @@ static void inject_llc(unsigned long long addr, void *vaddr, int notrigger) wfile(EINJ_NOTRIGGER, notrigger); wfile(EINJ_DOIT, 1); } + + +static void inject_cmn_fatal(unsigned long long addr, void *vaddr, int notrigger) { + PRINT_INJECTING; + wfile(EINJ_ETYPE, 0x800); + wfile(EINJ_MASK, 0x01); + wfile(EINJ_FLAGS, 0x01); + wfile(EINJ_NOTRIGGER, notrigger); + wfile(EINJ_DOIT, 1); +} + +static void inject_gic_ce(unsigned long long addr, void *vaddr, int notrigger) { + PRINT_INJECTING; + wfile(EINJ_ETYPE, 0x200); + wfile(EINJ_MASK, 0x02); + wfile(EINJ_FLAGS, 0x01); + wfile(EINJ_NOTRIGGER, notrigger); + wfile(EINJ_DOIT, 1); +} + +static void inject_gic_non_fatal(unsigned long long addr, void *vaddr, int notrigger) { + PRINT_INJECTING; + wfile(EINJ_ETYPE, 0x400); + wfile(EINJ_MASK, 0x02); + wfile(EINJ_FLAGS, 0x01); + wfile(EINJ_NOTRIGGER, notrigger); + wfile(EINJ_DOIT, 1); +} + +static void inject_smmu_tcu_ce(unsigned long long addr, void *vaddr, int notrigger) { + PRINT_INJECTING; + wfile(EINJ_ETYPE, 0x200); + wfile(EINJ_MASK, 0x03); + wfile(EINJ_FLAGS, 0x01); + wfile(EINJ_NOTRIGGER, notrigger); + wfile(EINJ_DOIT, 1); +} + +static void inject_smmu_tcu_non_fatal(unsigned long long addr, void *vaddr, int notrigger) { + PRINT_INJECTING; + wfile(EINJ_ETYPE, 0x400); + wfile(EINJ_MASK, 0x03); + wfile(EINJ_FLAGS, 0x01); + wfile(EINJ_NOTRIGGER, notrigger); + wfile(EINJ_DOIT, 1); +} + +static void inject_smmu_tcu_fatal(unsigned long long addr, void *vaddr, int notrigger) { + PRINT_INJECTING; + wfile(EINJ_ETYPE, 0x800); + wfile(EINJ_MASK, 0x03); + wfile(EINJ_FLAGS, 0x01); + wfile(EINJ_NOTRIGGER, notrigger); + wfile(EINJ_DOIT, 1); +} + +static void inject_smmu_tbu_ce(unsigned long long addr, void *vaddr, int notrigger) { + PRINT_INJECTING; + wfile(EINJ_ETYPE, 0x200); + wfile(EINJ_MASK, 0x04); + wfile(EINJ_FLAGS, 0x01); + wfile(EINJ_NOTRIGGER, notrigger); + wfile(EINJ_DOIT, 1); +} + +static void inject_smmu_tbu_non_fatal(unsigned long long addr, void *vaddr, int notrigger) { + PRINT_INJECTING; + wfile(EINJ_ETYPE, 0x400); + wfile(EINJ_MASK, 0x04); + wfile(EINJ_FLAGS, 0x01); + wfile(EINJ_NOTRIGGER, notrigger); + wfile(EINJ_DOIT, 1); +} + +static void inject_smmu_tbu_fatal(unsigned long long addr, void *vaddr, int notrigger) { + PRINT_INJECTING; + wfile(EINJ_ETYPE, 0x800); + wfile(EINJ_MASK, 0x04); + wfile(EINJ_FLAGS, 0x01); + wfile(EINJ_NOTRIGGER, notrigger); + wfile(EINJ_DOIT, 1); +} #endif static int is_privileged(void) @@ -697,6 +779,46 @@ struct test { }, #ifdef __aarch64__ { + "cmn_non_fatal", "CMN SLC Data RAM DE. Should generate a UCNA/CMCI", + data_alloc, inject_llc, 1, trigger_single, F_CMCI, + }, + { + "cmn_fatal", "CMN SLC Data RAM UE. Should fatal", + data_alloc, inject_cmn_fatal, 1, trigger_single, F_FATAL, + }, + { + "gic_ce", "GIC corrected error. Should generate a CMCI", + data_alloc, inject_gic_ce, 1, trigger_single, F_CMCI, + }, + { + "gic_non_fatal", "GIC deferred error", + data_alloc, inject_gic_non_fatal, 1, trigger_single, F_CMCI, + }, + { + "smmu_tcu_ce", "SMMU TCU corrected error. Should generate a UCNA/CMCI", + data_alloc, inject_smmu_tcu_ce, 1, trigger_single, F_CMCI, + }, + { + "smmu_tcu_non_fatal", "SMMU TCU deferred error. Should generate a UCNA/CMCI", + data_alloc, inject_smmu_tcu_non_fatal, 1, trigger_single, F_CMCI, + }, + { + "smmu_tcu_fatal", "SMMU TCU uncorrected error. Should fatal", + data_alloc, inject_smmu_tcu_fatal, 1, trigger_single, F_FATAL, + }, + { + "smmu_tbu_ce", "SMMU TBU corrected error. Should generate a UCNA/CMCI", + data_alloc, inject_smmu_tbu_ce, 1, trigger_single, F_CMCI, + }, + { + "smmu_tbu_non_fatal", "SMMU TBU deferred error. Should generate a UCNA/CMCI", + data_alloc, inject_smmu_tbu_non_fatal, 1, trigger_single, F_CMCI, + }, + { + "smmu_tbu_fatal", "SMMU TBU uncorrected error. Should fatal", + data_alloc, inject_smmu_tbu_fatal, 1, trigger_single, F_FATAL, + }, + { "strbyte", "Write to target address. Should generate a UCNA/CMCI", data_alloc, inject_uc, 1, trigger_write_byte, F_CMCI, }, |