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| author | Pekka Enberg <penberg@kernel.org> | 2012-04-27 21:53:32 +0300 |
|---|---|---|
| committer | Pekka Enberg <penberg@kernel.org> | 2012-04-27 21:53:32 +0300 |
| commit | 50a46ef6319d7c7dd2a9eba24f92986c4dfea62d (patch) | |
| tree | 1a3c167b112ab2f22d258c6006f876bcd14bdd12 | |
| parent | 905e20cf98fb159a50523e79bdfc38930546e3a4 (diff) | |
| download | jato-50a46ef6319d7c7dd2a9eba24f92986c4dfea62d.tar.gz | |
x86-64: Fix formatting in registers_64.c
Signed-off-by: Pekka Enberg <penberg@kernel.org>
| -rw-r--r-- | arch/x86/registers_64.c | 52 |
1 files changed, 26 insertions, 26 deletions
diff --git a/arch/x86/registers_64.c b/arch/x86/registers_64.c index 6a86c283..c85eb0fe 100644 --- a/arch/x86/registers_64.c +++ b/arch/x86/registers_64.c @@ -130,42 +130,42 @@ const char *reg_name(enum machine_reg reg) return register_names[reg]; } -#define GPR_64 (1UL << J_LONG) | (1UL << J_REFERENCE) -#define GPR_32 (1UL << J_INT) -#define GPR_16 (1UL << J_SHORT) | (1UL << J_CHAR) -#define GPR_8 (1UL << J_BYTE) | (1UL << J_BOOLEAN) -#define FPU (1UL << J_FLOAT) | (1UL << J_DOUBLE) +#define GPR_64 ((1UL << J_LONG) | (1UL << J_REFERENCE)) +#define GPR_32 ((1UL << J_INT) ) +#define GPR_16 ((1UL << J_SHORT) | (1UL << J_CHAR) ) +#define GPR_8 ((1UL << J_BYTE) | (1UL << J_BOOLEAN) ) +#define FPU ((1UL << J_FLOAT) | (1UL << J_DOUBLE) ) bool reg_supports_type(enum machine_reg reg, enum vm_type type) { static const uint32_t table[NR_REGISTERS] = { - [MACH_REG_RAX] = GPR_64 | GPR_32 | GPR_16 | GPR_8, - [MACH_REG_RCX] = GPR_64 | GPR_32 | GPR_16 | GPR_8, - [MACH_REG_RDX] = GPR_64 | GPR_32 | GPR_16 | GPR_8, - [MACH_REG_RBX] = GPR_64 | GPR_32 | GPR_16 | GPR_8, - [MACH_REG_R8] = GPR_64 | GPR_32 | GPR_16 | GPR_8, - [MACH_REG_R9] = GPR_64 | GPR_32 | GPR_16 | GPR_8, - [MACH_REG_R10] = GPR_64 | GPR_32 | GPR_16 | GPR_8, - [MACH_REG_R11] = GPR_64 | GPR_32 | GPR_16 | GPR_8, - [MACH_REG_R12] = GPR_64 | GPR_32 | GPR_16 | GPR_8, - [MACH_REG_R13] = GPR_64 | GPR_32 | GPR_16 | GPR_8, - [MACH_REG_R14] = GPR_64 | GPR_32 | GPR_16 | GPR_8, - [MACH_REG_R15] = GPR_64 | GPR_32 | GPR_16 | GPR_8, + [MACH_REG_RAX] = GPR_64 | GPR_32 | GPR_16 | GPR_8, + [MACH_REG_RCX] = GPR_64 | GPR_32 | GPR_16 | GPR_8, + [MACH_REG_RDX] = GPR_64 | GPR_32 | GPR_16 | GPR_8, + [MACH_REG_RBX] = GPR_64 | GPR_32 | GPR_16 | GPR_8, + [MACH_REG_R8 ] = GPR_64 | GPR_32 | GPR_16 | GPR_8, + [MACH_REG_R9 ] = GPR_64 | GPR_32 | GPR_16 | GPR_8, + [MACH_REG_R10] = GPR_64 | GPR_32 | GPR_16 | GPR_8, + [MACH_REG_R11] = GPR_64 | GPR_32 | GPR_16 | GPR_8, + [MACH_REG_R12] = GPR_64 | GPR_32 | GPR_16 | GPR_8, + [MACH_REG_R13] = GPR_64 | GPR_32 | GPR_16 | GPR_8, + [MACH_REG_R14] = GPR_64 | GPR_32 | GPR_16 | GPR_8, + [MACH_REG_R15] = GPR_64 | GPR_32 | GPR_16 | GPR_8, /* XXX: We can't access the lower nibbles of these registers, * so they shouldn't have GPR_16 or GPR_8, but we need it for * now to work around a reg-alloc bug. */ - [MACH_REG_RSI] = GPR_64 | GPR_32 | GPR_16 | GPR_8, - [MACH_REG_RDI] = GPR_64 | GPR_32 | GPR_16 | GPR_8, + [MACH_REG_RSI] = GPR_64 | GPR_32 | GPR_16 | GPR_8, + [MACH_REG_RDI] = GPR_64 | GPR_32 | GPR_16 | GPR_8, - [MACH_REG_XMM0] = FPU, - [MACH_REG_XMM1] = FPU, - [MACH_REG_XMM2] = FPU, + [MACH_REG_XMM0] = FPU, + [MACH_REG_XMM1] = FPU, + [MACH_REG_XMM2] = FPU, [MACH_REG_XMM3] = FPU, - [MACH_REG_XMM4] = FPU, - [MACH_REG_XMM5] = FPU, - [MACH_REG_XMM6] = FPU, - [MACH_REG_XMM7] = FPU, + [MACH_REG_XMM4] = FPU, + [MACH_REG_XMM5] = FPU, + [MACH_REG_XMM6] = FPU, + [MACH_REG_XMM7] = FPU, }; assert(reg < NR_REGISTERS); |