Skip to main content

_tile_loadconfig

Function _tile_loadconfig 

Source
pub unsafe fn _tile_loadconfig(mem_addr: *const u8)
🔬This is a nightly-only experimental API. (x86_amx_intrinsics #126622)
Available on x86-64 and target feature amx-tile only.
Expand description

Load tile configuration from a 64-byte memory location specified by mem_addr. The tile configuration format is specified below, and includes the tile type pallette, the number of bytes per row, and the number of rows. If the specified pallette_id is zero, that signifies the init state for both the tile config and the tile data, and the tiles are zeroed. Any invalid configurations will result in #GP fault.

//	format of memory payload. each field is a byte.
	 0: palette
	 1: start_row
  2-15: reserved, must be zero
 16-17: tile0.colsb
 18-19: tile1.colsb
 20-21: tile2.colsb
		...
 30-31: tile7.colsb
 32-47: reserved, must be zero
	48: tile0.rows
	49: tile1.rows
	50: tile2.rows
		 ...
	55: tile7.rows
 56-63: reserved, must be zero

Intel’s documentation