# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/usb/st,stm32mp25-dwc3.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 MPU DWC3 USB SoC controller description: The STM32 MPU DWC3 USB SoC controller block supports both Host(SS/HS/FS/LS) and Device(SS/HS/FS) mode operation maintainers: - Fabrice Gasnier - Marek Vasut allOf: - $ref: snps,dwc3-common.yaml# properties: compatible: const: st,stm32mp25-dwc3 reg: maxItems: 1 access-controllers: maxItems: 1 clocks: minItems: 3 maxItems: 3 clock-names: items: - const: ref - const: bus_early - const: suspend interrupts: maxItems: 1 resets: maxItems: 1 over-current-active-low: type: boolean description: Over-Current signal polarity is active-low st,syscfg: $ref: /schemas/types.yaml#/definitions/phandle-array description: Phandle to system configuration controller. items: - items: - description: phandle to syscfg - description: USB3DR control offset within syscfg st,enable-port-power-control: type: boolean description: Enable Host-Mode Port Power Control (bit-3 of capability param HCCPARAMS) st,vbusen-active-low: type: boolean description: VBUS-ENABLE signal polarity is active-low required: - compatible - reg - clocks - clock-names - interrupts - phys - phy-names - resets - st,syscfg unevaluatedProperties: false examples: - | #include #include #include usb@48300000 { compatible = "st,stm32mp25-dwc3"; reg = <0x48300000 0x100000>; clocks = <&rcc CK_KER_USB2PHY2>, <&rcc CK_BUS_USB3DR>, <&rcc CK_KER_USB2PHY2>; clock-names = "ref", "bus_early", "suspend"; interrupts = ; phys = <&usb2_phy>, <&usb3_phy>; phy-names = "usb2-phy", "usb3-phy"; resets = <&rcc USB3DR_R>; over-current-active-low; st,syscfg = <&syscfg 0x4800>; st,vbusen-active-low; };