# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/sound/qcom,shikra-qaif-cpu.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Audio Interface (QAIF) CPU DAI Controller maintainers: - Harendra Gautam description: | The Qualcomm Audio Interface (QAIF) is a fully configurable DMA-based audio subsystem controller. It serialises and deserialises PCM audio between system memory and external serial audio peripherals (PCM, TDM, I2S, MI2S) through the AIF path, and transfers parallel audio between memory and an internal WCD codec through the CIF path. AIF (Audio Interface): up to 13 multi-lane Unified Audio Interfaces, each supporting up to 8 independent data lanes. Each lane is individually configurable as TX (output/speaker) or RX (input/mic). All lanes of an interface share a single bit clock and frame sync. Supported modes are PCM (short/long sync), TDM, and MI2S (stereo/mono). Per-interface configuration includes sync source (master/slave), sync mode, sync delay, sync inversion, slot width (8/16/24/32-bit), sample width, active slot masks (up to 32 slots), bits-per-lane frame size, lane enable/direction masks, loopback, output-enable control, and full-cycle path support for long chip-to-chip connections. CIF (Codec Interface): up to 10 RDDMA (playback) and 10 WRDMA (capture) channels connecting to an internal codec over a parallel bus. Each channel supports active-channel enable mask (up to 16 channels), frame-sync selection, frame-sync delay, frame-sync output gating, dynamic clock gating, and 16-bit packing/unpacking. Note on RX/TX naming convention: in QAIF, TX refers to the output (speaker/playback) direction and RX refers to the input (mic/capture) direction. This applies to both AIF lane directions and CIF slot/mask properties. DMA engine: RDDMA fetches audio from DDR/TCM/LPM into a shared SRAM latency buffer (SHRAM) and drains it to the interface. WRDMA collects data from the interface into SHRAM and writes it to memory. Each DMA owns a private SHRAM region defined by start address and length registers. Burst sizes of 1/2/4/8/16 beats (64-bit) are supported with up to 4 outstanding transactions per DMA. Two QSB master ports (QXM0 for TCM, QXM1 for DDR/LPM) provide the memory interface. Resources are partitioned among up to 5 Execution Engines (EEs) via EE map registers. Each EE owns a set of DMAs, audio interfaces, and interface groups, and receives its own independent interrupt output. The interrupt hierarchy has a two-level structure: a summary register identifies the event class (DMA period, underflow/overflow, error response, audio interface underflow/overflow, group done, rate detector, VFR), and per-resource status registers identify the specific channel. Interface grouping (bonding) allows up to 6 groups of audio and codec interfaces to start synchronously and align their DMA period interrupts within half a frame duration using the RDDMA padding feature. Two rate detector blocks measure the frequency of incoming frame sync or word select signals and generate interrupts on rate change, undetected rate, or sync timeout. Block diagram:: System Memory (DDR / LPM / TCM) +---------------------------------+ | Circular Buffers (ping-pong) | +----------+----------+-----------+ | ^ 64-bit AXI 64-bit AXI | | +----------v----------+-----------+ | QSB Master Ports | | +----------+ +----------+ | | | QXM0 | | QXM1 | | | +----+-----+ +-----+----+ | +-------|--------------|----------+ | | +-------v--------------v----------+ | Shared RAM (SHRAM) | | +------------+ +------------+ | | | QXM0 Read | | QXM0 Write | | | | SHRAM | | SHRAM | | | +------------+ +------------+ | | +------------+ +------------+ | | | QXM1 Read | | QXM1 Write | | | | SHRAM | | SHRAM | | | +------------+ +------------+ | +---+--------+--------+-------+---+ | | | | +---v--+ +--v---+ +--v---+ +-v----+ |RDDMA | |RDDMA | |WRDMA | |WRDMA | | AIF | | CIF | | AIF | | CIF | |[0..n]| |[0..n]| |[0..n]| |[0..n]| +--+---+ +--+---+ +--+---+ +-+----+ | | ^ ^ | TX | TX | RX | RX v v | | +--+--------------------+ +----+----------+ | Unified Audio Intf | | Codec DMA | | (AIF 0..12) | | Interface | | | | (CIF) | | AUD_INTFa block: | | | | - Serializer (TX) | | RDDMA: DDR -> | | - De-serializer (RX) | | internal | | - Sync gen/detect | | codec | | - Up to 8 data lanes | | WRDMA: codec | | - PCM / TDM / MI2S | | -> DDR | | - Near Pad Logic | | Up to 16 ch | +--+--------------------+ +----+----------+ | Lane 0..7 (TX/RX) | Parallel bus | Bit clk + Frame sync | + Frame sync v v +--+--------+ +------+------+ | External | | Internal | | Serial | | Digital | | Peripherals| | Codec | | (PCM/TDM/ | | (Bolero/ | | MI2S) | | WCD) | +-----------+ +-------------+ allOf: - $ref: dai-common.yaml# properties: compatible: const: qcom,shikra-qaif-cpu reg: maxItems: 1 interrupts: maxItems: 1 description: QAIF summary interrupt for this Execution Engine. iommus: maxItems: 1 dma-coherent: true clocks: maxItems: 9 clock-names: description: Core clocks for register access and DMA, followed by one bit clock per AIF interface. items: - const: lpass_config - const: lpass_core_axim - const: aud_dma - const: aud_dma_mem - const: bus - const: aif_if0_ibit - const: aif_if1_ibit - const: aif_if2_ibit - const: aif_if3_ibit '#sound-dai-cells': const: 1 '#address-cells': const: 1 '#size-cells': const: 0 patternProperties: '^aif@[0-9a-f]+$': type: object description: QAIF AIF interface child node for PCM, TDM or MI2S configuration. allOf: - $ref: /schemas/sound/tdm-slot.yaml# properties: reg: maxItems: 1 description: DAI ID of the AIF interface (QAIF_MI2S_AIF* or QAIF_TDM_AIF*). dai-format: description: Serial audio interface format (MI2S, TDM or PCM). enum: [i2s, dsp_a, dsp_b] dai-tdm-slot-width: enum: [8, 16, 24, 32] dai-tdm-slot-num: minimum: 1 maximum: 32 dai-tdm-slot-rx-mask: minItems: 1 maxItems: 32 dai-tdm-slot-tx-mask: minItems: 1 maxItems: 32 qcom,qaif-aif-lane-map: $ref: /schemas/types.yaml#/definitions/uint32-array description: Per-lane direction map, one entry per lane starting from lane 0. Use 0 for TX (output/speaker) and 1 for RX (input/mic). minItems: 1 maxItems: 8 items: enum: [0, 1] required: - reg - dai-format - qcom,qaif-aif-lane-map if: properties: dai-format: enum: [dsp_a, dsp_b] then: required: - dai-tdm-slot-width - dai-tdm-slot-num - dai-tdm-slot-rx-mask - dai-tdm-slot-tx-mask unevaluatedProperties: false required: - compatible - reg - interrupts - iommus - clocks - clock-names - '#sound-dai-cells' - '#address-cells' - '#size-cells' unevaluatedProperties: false examples: - | #include soc { #address-cells = <2>; #size-cells = <2>; qaif_cpu: audio-controller@a000000 { compatible = "qcom,shikra-qaif-cpu"; reg = <0x0 0x0a000000 0x0 0x20000>; interrupts = ; iommus = <&apps_smmu 0x1c0 0x0>; clocks = <&gcc 213>, <&gcc 214>, <&audiocorecc 15>, <&audiocorecc 17>, <&audiocorecc 18>, <&audiocorecc 5>, <&audiocorecc 8>, <&audiocorecc 11>, <&audiocorecc 14>; clock-names = "lpass_config", "lpass_core_axim", "aud_dma", "aud_dma_mem", "bus", "aif_if0_ibit", "aif_if1_ibit", "aif_if2_ibit", "aif_if3_ibit"; #sound-dai-cells = <1>; #address-cells = <1>; #size-cells = <0>; aif@b5 { reg = <181>; dai-format = "dsp_a"; dai-tdm-slot-width = <32>; dai-tdm-slot-num = <2>; dai-tdm-slot-rx-mask = <1 1>; dai-tdm-slot-tx-mask = <1 1>; qcom,qaif-aif-lane-map = <1 0>; }; }; };