# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/cix/cix,sky1-audss-cru.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Cix Sky1 audio subsystem clock and reset unit

maintainers:
  - Joakim Zhang <joakim.zhang@cixtech.com>

description: |
  The Cix Sky1 Audio Subsystem (AUDSS) Clock and Reset Unit (CRU) groups
  audio-related clock muxing, gating and block-level software reset control
  in a single register block.

  A single device node exposes both the clock controller and software reset
  lines. The clock driver registers as a platform driver; the reset controller
  is registered by an auxiliary driver bound from the clock driver.

  Four SoC-level reference clocks listed in clocks/clock-names feed the AUDSS
  clock tree. Internal AUDSS clocks are exposed via #clock-cells; indices are
  defined in include/dt-bindings/clock/cix,sky1-audss-cru.h.

  Block-level software reset indices are exposed via #reset-cells; indices
  are defined in include/dt-bindings/reset/cix,sky1-audss-cru.h.

  The SoC syscon NoC (or bus) reset is described via resets. The audio
  subsystem power domain is described via power-domains.

properties:
  compatible:
    const: cix,sky1-audss-cru

  reg:
    maxItems: 1

  '#clock-cells':
    const: 1
    description:
      Clock indices are defined in include/dt-bindings/clock/cix,sky1-audss-cru.h.

  '#reset-cells':
    const: 1
    description:
      Reset indices are defined in include/dt-bindings/reset/cix,sky1-audss-cru.h.

  clocks:
    items:
      - description: I2S parent clock for sampling rates multiple of 8kHz.
      - description: I2S parent clock for sampling rates multiple of 11.025kHz.
      - description: Clock feeding most devices in AUDSS (NOC, DSP, SRAM, HDA, DMAC, I2S, and mailbox).
      - description: Clock feeding HDA, timer and watchdog, which is a dedicated 48 MHz clock.

  clock-names:
    items:
      - const: x8k
      - const: x11k
      - const: sys
      - const: 48m

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

required:
  - compatible
  - reg
  - '#clock-cells'
  - '#reset-cells'
  - clocks
  - clock-names
  - power-domains
  - resets

additionalProperties: false

examples:
  - |
    audss_cru: clock-controller@7110000 {
        compatible = "cix,sky1-audss-cru";
        reg = <0x7110000 0x10000>;
        #clock-cells = <1>;
        #reset-cells = <1>;
        clocks = <&scmi_clk 76>, <&scmi_clk 78>,
                 <&scmi_clk 70>, <&scmi_clk 71>;
        clock-names = "x8k", "x11k", "sys", "48m";
        power-domains = <&smc_devpd 0>;
        resets = <&s5_syscon 31>;
    };