# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-sys1-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: StarFive JHB100 System-1 Pin Controller

description: |
  Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd.

  The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1,
  per2, per2pok, per3, adc0, adc1, emmc, and vga.
  This document provides an overview of the "sys1" pinctrl domain.

  The "sys1" domain has a pin controller which provides
  - function selection for GPIO pads.
  - GPIO pad configuration.
  - GPIO interrupt handling.

  In the SYS1 Pin Controller, there are 8 multi-function GPIO_PADs. Each of
  them can be multiplexed to different hardware blocks through function
  selection. Each iopad has a maximum of up to 4 functions - 0, 1, 2, and 3.
  Function 0 is the default function which is generally the GPIO function
  (or occasionally, it can be a peripheral signal).
  Function 1, 2, and 3 are the alternate functions or peripheral signals that
  can be routed to the iopad. The function selection can be carried out by
  writing the function number to the iopad function select register.

  Each iopad is configurable with parameters such as input-enable, internal
  pull-up/pull-down bias, drive strength, schmitt trigger, slew rate, input
  debounce nanoseconds.

maintainers:
  - Changhuang Liang <changhuang.liang@starfivetech.com>

properties:
  compatible:
    items:
      - const: starfive,jhb100-sys1-pinctrl

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  resets:
    maxItems: 1

  interrupts:
    maxItems: 1

  interrupt-controller: true

  '#interrupt-cells':
    const: 2

  gpio-controller: true

  '#gpio-cells':
    const: 2

  gpio-ranges: true

  gpio-line-names: true

patternProperties:
  '-grp$':
    type: object
    additionalProperties: false
    patternProperties:
      '-pins$':
        type: object
        description: |
          A pinctrl node should contain at least one subnode representing the
          pinctrl groups available in the domain. Each subnode will list the
          pins it needs, and how they should be configured, with regard to
          function selection, bias, input enable/disable, input schmitt
          trigger enable/disable, slew-rate, input debounce nanoseconds
          and drive-strength.
        allOf:
          - $ref: /schemas/pinctrl/pincfg-node.yaml
          - $ref: /schemas/pinctrl/pinmux-node.yaml
        additionalProperties: false

        properties:
          pins:
            description:
              The list of IOs that properties in the pincfg node apply to.

          function:
            description:
              A string containing the name of the function to mux for these
              pins.
            enum: [ espi, espi_reset, gpio, host0_port80, host1_port80 ]

          bias-disable: true

          bias-pull-down:
            type: boolean

          bias-pull-up:
            type: boolean

          drive-strength:
            enum: [ 2, 4, 8, 12 ]

          drive-strength-microamp:
            enum: [ 2000, 4000, 8000, 12000 ]

          input-debounce-ns:
            minimum: 0
            maximum: 10485680
            description:
              Debounce time in nanoseconds. The hardware counts in 80 ns
              stages with a 17-bit counter, so the maximum is 10485680 ns.

          input-disable: true

          input-enable: true

          input-schmitt-enable: true

          input-schmitt-disable: true

          slew-rate:
            enum: [ 0, 1 ]
            default: 0
            description: |
                0: slow
                1: fast

required:
  - compatible
  - reg
  - resets
  - interrupts
  - interrupt-controller
  - '#interrupt-cells'
  - gpio-controller
  - '#gpio-cells'
  - gpio-ranges

additionalProperties: false

examples:
  - |
    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        pinctrl_sys1: pinctrl@13081000 {
            compatible = "starfive,jhb100-sys1-pinctrl";
            reg = <0x0 0x13081000 0x0 0x1000>;
            resets = <&sys1crg 2>;
            interrupts = <58>;
            interrupt-controller;
            #interrupt-cells = <2>;
            gpio-controller;
            #gpio-cells = <2>;
            gpio-ranges = <&pinctrl_sys1 0 0 8>;
        };
    };