# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,shikra-tlmm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies, Inc. Shikra TLMM block

maintainers:
  - Komal Bajaj <komal.bajaj@oss.qualcomm.com>

description: |
  Top Level Mode Multiplexer pin controller in Qualcomm Shikra SoC.

allOf:
  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#

properties:
  compatible:
    const: qcom,shikra-tlmm

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  gpio-reserved-ranges:
    minItems: 1
    maxItems: 83

  gpio-line-names:
    maxItems: 166

patternProperties:
  "-state$":
    oneOf:
      - $ref: "#/$defs/qcom-shikra-tlmm-state"
      - patternProperties:
          "-pins$":
            $ref: "#/$defs/qcom-shikra-tlmm-state"
        additionalProperties: false

$defs:
  qcom-shikra-tlmm-state:
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.
    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
    unevaluatedProperties: false

    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in this
          subnode.
        items:
          oneOf:
            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-5][0-9]|16[0-5])$"
            - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data,
                      sdc2_clk, sdc2_cmd, sdc2_data ]
        minItems: 1
        maxItems: 36

      function:
        description:
          Specify the alternative function to be configured for the specified
          pins.

        enum: [ gpio, agera_pll, atest_bbrx, atest_char, atest_gpsadc,
                atest_tsens, atest_usb, cam_mclk, cci_async, cci_i2c0,
                cci_i2c1, cci_timer, char_exec, cri_trng, dac_calib,
                dbg_out_clk, ddr_bist, ddr_pxi, dmic, emac_dll, emac_mcg,
                emac_phy, emac0_ptp_aux, emac0_ptp_pps, emac1_ptp_aux,
                emac1_ptp_pps, ext_mclk, gcc_gp, gsm0_tx, i2s0, i2s1,
                i2s2, i2s3, jitter_bist, m_voc, mdp_vsync_e, mdp_vsync_out0,
                mdp_vsync_out1, mdp_vsync_p, mdp_vsync_s, mpm_pwr, mss_lte,
                nav_gpio, pa_indicator_or, pbs_in, pbs_out, pcie0_clk_req_n,
                phase_flag, pll, prng_rosc, pwm, qdss_cti, qup0_se0,
                qup0_se1, qup0_se1_01, qup0_se1_23, qup0_se2, qup0_se3_01,
                qup0_se3_23, qup0_se4_01, qup0_se4_23, qup0_se5, qup0_se6,
                qup0_se7_01, qup0_se7_23, qup0_se8, qup0_se9, qup0_se9_01,
                qup0_se9_23, rgmii, sd_write_protect, sdc_cdc, sdc_tb_trig,
                ssbi_wtr, swr0_rx, swr0_tx, tgu_ch_trigout, tsc_async,
                tsense_pwm, uim1, uim2, unused_adsp, unused_gsm1, usb0_phy_ps,
                vfr, vsense_trigger_mirnat, wlan ]

    required:
      - pins

required:
  - compatible
  - reg

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    tlmm: pinctrl@500000 {
        compatible = "qcom,shikra-tlmm";
        reg = <0x00500000 0x800000>;

        interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;

        gpio-controller;
        #gpio-cells = <2>;

        interrupt-controller;
        #interrupt-cells = <2>;

        gpio-ranges = <&tlmm 0 0 166>;

        qup-uart0-default-state {
            pins = "gpio0", "gpio1";
            function = "qup0_se1";
            drive-strength = <2>;
            bias-disable;
        };
    };
...