# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/qcom,x1e80100-csi2-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm X1E80100 SoC CSI2 PHY

maintainers:
  - Bryan O'Donoghue <bod@kernel.org>

description:
  Qualcomm MIPI CSI2 C-PHY/D-PHY combination PHY. Connects MIPI CSI2 sensors
  to Qualcomm's Camera CSI Decoder. The PHY supports both C-PHY and D-PHY
  modes.

properties:
  compatible:
    oneOf:
      - const: qcom,x1e80100-csi2-phy
      - items:
          - const: qcom,glymur-csi2-phy
          - const: qcom,x1e80100-csi2-phy

  reg:
    maxItems: 1

  clocks:
    maxItems: 3

  clock-names:
    items:
      - const: core
      - const: timer
      - const: ahb

  interrupts:
    maxItems: 1

  operating-points-v2: true

  opp-table:
    type: object

  power-domains:
    items:
      - description: Titan Top GDSC - Titan ISP Block, Global Distributed Switch Controller.
      - description: MMCX voltage rail
      - description: MXC or MXA voltage rail

  power-domain-names:
    items:
      - const: top
      - const: mmcx
      - const: mx

  vdda-0p9-supply:
    description: Phandle to a 0.9V regulator supply to a PHY.

  vdda-1p2-supply:
    description: Phandle to 1.2V regulator supply to a PHY.

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/$defs/port-base
        description:
          Sensor input. Always present. A single sensor is described by a
          single endpoint with one to four data lanes, numbered 1-4. The
          clock lane is position 0.

          DPHY split mode, where two independent sensors share the PHY, is
          described by two endpoints. endpoint@0 uses data lanes 1 or 1-2,
          clock lane position 0; endpoint@1 uses data lane 3, clock lane
          position 4.

        unevaluatedProperties: false

        patternProperties:
          "^endpoint(@[01])?$":
            $ref: /schemas/media/video-interfaces.yaml#
            unevaluatedProperties: false
            properties:
              bus-type:
                enum:
                  - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
                  - 4 # MEDIA_BUS_TYPE_CSI2_DPHY
                default: 4

              data-lanes:
                minItems: 1
                maxItems: 4
                items:
                  minimum: 1
                  maximum: 4
                description:
                  Data lane positions following this endpoint's clock
                  lane. Positions are a per-port logical numbering, not
                  package pad or ball positions.

            required:
              - data-lanes
              - remote-endpoint

        allOf:
          - if:
              required:
                - endpoint@1
            then:
              properties:
                endpoint@0:
                  properties:
                    data-lanes:
                      maxItems: 2
                      items:
                        maximum: 2
                endpoint@1:
                  properties:
                    data-lanes:
                      items:
                        - const: 3
              required:
                - endpoint@0

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description: Output to the CAMSS CSID controller.

    required:
      - port@0
      - port@1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - interrupts
  - operating-points-v2
  - power-domains
  - power-domain-names
  - vdda-0p9-supply
  - vdda-1p2-supply
  - ports

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,x1e80100-camcc.h>
    #include <dt-bindings/clock/qcom,x1e80100-gcc.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/media/video-interfaces.h>
    #include <dt-bindings/power/qcom,rpmhpd.h>

    phy@ace4000 {
        compatible = "qcom,x1e80100-csi2-phy";
        reg = <0x0ace4000 0x2000>;

        clocks = <&camcc CAM_CC_CSIPHY0_CLK>,
                 <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
                 <&camcc CAM_CC_CORE_AHB_CLK>;
        clock-names = "core",
                      "timer",
                      "ahb";

        interrupts = <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>;

        operating-points-v2 = <&csiphy_opp_table>;

        power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>,
                        <&rpmhpd RPMHPD_MMCX>,
                        <&rpmhpd RPMHPD_MX>;
        power-domain-names = "top",
                             "mmcx",
                             "mx";

        vdda-0p9-supply = <&vreg_l2c_0p9>;
        vdda-1p2-supply = <&vreg_l1c_1p2>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                reg = <0>;
                csiphy0_in: endpoint {
                    bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
                    data-lanes = <1 2 3 4>;
                    remote-endpoint = <&sensor_out>;
                };
            };

            port@1 {
                reg = <1>;
                csiphy0_out: endpoint {
                    remote-endpoint = <&csid_in>;
                };
            };
        };

        csiphy_opp_table: opp-table {
            compatible = "operating-points-v2";

            opp-300000000 {
                opp-hz = /bits/ 64 <300000000>;
                required-opps = <&rpmhpd_opp_low_svs_d1>,
                                <&rpmhpd_opp_low_svs_d1>;
            };
        };
    };