# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/mediatek,mt8195-dp-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek SoC DisplayPort Transmitter PHY

maintainers:
  - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

properties:
  compatible:
    enum:
      - mediatek,mt8195-dp-phy
      - mediatek,mt8196-edp-phy

  reg:
    maxItems: 1

  "#phy-cells":
    const: 0

  nvmem-cells:
    description: PHY calibrations from eFuse for optimal EYE signal pattern
    items:
      - description: PHY-Global Reference Bias trim
      - description: PHY-Global AUX Transmitter clock impedance adjustment
      - description: Lane 0 Transmitter impedance selection (P-MOSFET)
      - description: Lane 0 Transmitter impedance selection (N-MOSFET)
      - description: Lane 1 Transmitter impedance selection (P-MOSFET)
      - description: Lane 1 Transmitter impedance selection (N-MOSFET)
      - description: Lane 2 Transmitter impedance selection (P-MOSFET)
      - description: Lane 2 Transmitter impedance selection (N-MOSFET)
      - description: Lane 3 Transmitter impedance selection (P-MOSFET)
      - description: Lane 3 Transmitter impedance selection (N-MOSFET)

  nvmem-cell-names:
    items:
      - const: rbias-trim
      - const: impedance-txclk
      - const: impedance-lane0p
      - const: impedance-lane0n
      - const: impedance-lane1p
      - const: impedance-lane1n
      - const: impedance-lane2p
      - const: impedance-lane2n
      - const: impedance-lane3p
      - const: impedance-lane3n

  power-domains:
    maxItems: 1

required:
  - compatible
  - reg
  - "#phy-cells"

additionalProperties: false

examples:
  - |
    phy@1c500000 {
        compatible = "mediatek,mt8195-dp-phy";
        reg = <0x1c500000 0x2000>;
        #phy-cells = <0>;
        nvmem-cells = <&edp_glb_bias_trim>, <&edp_clktx_impsel>,
                      <&edp_imp_ln0_pmos>, <&edp_imp_ln0_nmos>,
                      <&edp_imp_ln1_pmos>, <&edp_imp_ln1_nmos>,
                      <&edp_imp_ln2_pmos>, <&edp_imp_ln2_nmos>,
                      <&edp_imp_ln3_pmos>, <&edp_imp_ln3_nmos>;
        nvmem-cell-names = "rbias-trim", "impedance-txclk",
                           "impedance-lane0p", "impedance-lane0n",
                           "impedance-lane1p", "impedance-lane1n",
                           "impedance-lane2p", "impedance-lane2n",
                           "impedance-lane3p", "impedance-lane3n";
    };