# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/pci/qcom,pcie-apq8064.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm APQ8064/IPQ8064 PCI Express Root Complex maintainers: - Bjorn Andersson - Manivannan Sadhasivam properties: compatible: enum: - qcom,pcie-apq8064 - qcom,pcie-ipq8064 - qcom,pcie-ipq8064-v2 reg: maxItems: 4 reg-names: items: - const: dbi - const: elbi - const: parf - const: config clocks: minItems: 3 maxItems: 5 clock-names: minItems: 3 items: - const: core # Clocks the pcie hw block - const: iface # Configuration AHB clock - const: phy - const: aux - const: ref interrupts: maxItems: 1 interrupt-names: items: - const: msi resets: minItems: 5 maxItems: 6 reset-names: minItems: 5 items: - const: axi - const: ahb - const: por - const: pci - const: phy - const: ext vdda-supply: description: A phandle to the core analog power supply vdda_phy-supply: description: A phandle to the core analog power supply for PHY vdda_refclk-supply: description: A phandle to the core analog power supply for IC which generates reference clock required: - resets - reset-names - vdda-supply - vdda_phy-supply - vdda_refclk-supply allOf: - $ref: qcom,pcie-common.yaml# - if: properties: compatible: contains: enum: - qcom,pcie-apq8064 then: properties: clocks: maxItems: 3 clock-names: maxItems: 3 resets: maxItems: 5 reset-names: maxItems: 5 else: properties: clocks: minItems: 5 clock-names: minItems: 5 resets: minItems: 6 reset-names: minItems: 6 unevaluatedProperties: false examples: - | #include #include #include #include pcie@1b500000 { compatible = "qcom,pcie-apq8064"; reg = <0x1b500000 0x1000>, <0x1b502000 0x80>, <0x1b600000 0x100>, <0x0ff00000 0x100000>; reg-names = "dbi", "elbi", "parf", "config"; ranges = <0x81000000 0x0 0x00000000 0x0fe00000 0x0 0x00100000>, /* I/O */ <0x82000000 0x0 0x08000000 0x08000000 0x0 0x07e00000>; /* mem */ device_type = "pci"; linux,pci-domain = <0>; bus-range = <0x00 0xff>; num-lanes = <1>; #address-cells = <3>; #size-cells = <2>; clocks = <&gcc PCIE_A_CLK>, <&gcc PCIE_H_CLK>, <&gcc PCIE_PHY_REF_CLK>; clock-names = "core", "iface", "phy"; interrupts = ; interrupt-names = "msi"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ <0 0 0 2 &intc GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ <0 0 0 3 &intc GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ <0 0 0 4 &intc GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ resets = <&gcc PCIE_ACLK_RESET>, <&gcc PCIE_HCLK_RESET>, <&gcc PCIE_POR_RESET>, <&gcc PCIE_PCI_RESET>, <&gcc PCIE_PHY_RESET>; reset-names = "axi", "ahb", "por", "pci", "phy"; perst-gpios = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>; vdda-supply = <&pm8921_s3>; vdda_phy-supply = <&pm8921_lvs6>; vdda_refclk-supply = <&v3p3_fixed>; pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; #address-cells = <3>; #size-cells = <2>; ranges; }; };