# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie-ep.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: NVIDIA Tegra194 (and later) PCIe Endpoint controller (Synopsys DesignWare Core based) maintainers: - Thierry Reding - Jon Hunter - Vidya Sagar description: | This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus inherits all the common properties defined in snps,dw-pcie-ep.yaml. Some of the controller instances are dual mode; they can work either in Root Port mode or Endpoint mode but one at a time. On Tegra194, controllers C0, C4 and C5 support Endpoint mode. On Tegra234, controllers C5, C6, C7 and C10 support Endpoint mode. Note: On Tegra194's P2972-0000 platform, only C5 controller can be enabled to operate in the Endpoint mode because of the way the platform is designed. properties: compatible: enum: - nvidia,tegra194-pcie-ep - nvidia,tegra234-pcie-ep reg: items: - description: controller's application logic registers - description: iATU and DMA registers. This is where the iATU (internal Address Translation Unit) registers of the PCIe core are made available for software access. - description: aperture where the Root Port's own configuration registers are available. - description: aperture used to map the remote Root Complex address space reg-names: items: - const: appl - const: atu_dma - const: dbi - const: addr_space interrupts: items: - description: controller interrupt interrupt-names: items: - const: intr clocks: items: - description: module clock clock-names: items: - const: core resets: items: - description: APB bus interface reset - description: module reset reset-names: items: - const: apb - const: core reset-gpios: description: Must contain a phandle to a GPIO controller followed by GPIO that is being used as PERST input signal. Please refer to pci.txt. phys: minItems: 1 maxItems: 8 phy-names: minItems: 1 items: - const: p2u-0 - const: p2u-1 - const: p2u-2 - const: p2u-3 - const: p2u-4 - const: p2u-5 - const: p2u-6 - const: p2u-7 power-domains: maxItems: 1 description: | A phandle to the node that controls power to the respective PCIe controller and a specifier name for the PCIe controller. Tegra194 specifiers are defined in "include/dt-bindings/power/tegra194-powergate.h" Tegra234 specifiers are defined in "include/dt-bindings/power/tegra234-powergate.h" interconnects: items: - description: memory read client - description: memory write client interconnect-names: items: - const: dma-mem # read - const: write dma-coherent: true nvidia,bpmp: $ref: /schemas/types.yaml#/definitions/phandle-array description: | Must contain a pair of phandles to BPMP controller node followed by controller ID. Following are the controller IDs for each controller: Tegra194 0: C0 1: C1 2: C2 3: C3 4: C4 5: C5 Tegra234 0 : C0 1 : C1 2 : C2 3 : C3 4 : C4 5 : C5 6 : C6 7 : C7 8 : C8 9 : C9 10: C10 items: - items: - description: phandle to BPMP controller node - description: PCIe controller ID maximum: 10 nvidia,aspm-cmrt-us: description: Common Mode Restore Time for proper operation of ASPM to be specified in microseconds nvidia,aspm-pwr-on-t-us: description: Power On time for proper operation of ASPM to be specified in microseconds nvidia,aspm-l0s-entrance-latency-us: description: ASPM L0s entrance latency to be specified in microseconds vddio-pex-ctl-supply: description: A phandle to the regulator supply for PCIe side band signals nvidia,refclk-select-gpios: maxItems: 1 description: GPIO used to enable REFCLK to controller from the host nvidia,enable-ext-refclk: description: | This boolean property needs to be present if the controller is configured to receive Reference Clock from the host. NOTE: This is applicable only for Tegra234. $ref: /schemas/types.yaml#/definitions/flag nvidia,enable-srns: description: | This boolean property needs to be present if the controller is configured to operate in SRNS (Separate Reference Clocks with No Spread-Spectrum Clocking). NOTE: This is applicable only for Tegra234. $ref: /schemas/types.yaml#/definitions/flag allOf: - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# unevaluatedProperties: false required: - interrupts - interrupt-names - clocks - clock-names - resets - reset-names - power-domains - reset-gpios - vddio-pex-ctl-supply - num-lanes - phys - phy-names - nvidia,bpmp examples: - | #include #include #include #include #include bus@0 { #address-cells = <2>; #size-cells = <2>; ranges = <0x0 0x0 0x0 0x8 0x0>; pcie-ep@141a0000 { compatible = "nvidia,tegra194-pcie-ep"; reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ reg-names = "appl", "atu_dma", "dbi", "addr_space"; interrupts = ; /* controller interrupt */ interrupt-names = "intr"; clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; clock-names = "core"; resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, <&bpmp TEGRA194_RESET_PEX1_CORE_5>; reset-names = "apb", "core"; power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; pinctrl-names = "default"; pinctrl-0 = <&clkreq_c5_bi_dir_state>; nvidia,bpmp = <&bpmp 5>; nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; vddio-pex-ctl-supply = <&vdd_1v8ao>; reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>; nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5) GPIO_ACTIVE_HIGH>; num-lanes = <8>; phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, <&p2u_nvhs_6>, <&p2u_nvhs_7>; phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", "p2u-5", "p2u-6", "p2u-7"; }; }; - | #include #include #include #include #include bus@0 { #address-cells = <2>; #size-cells = <2>; ranges = <0x0 0x0 0x0 0x8 0x0>; pcie-ep@141a0000 { compatible = "nvidia,tegra234-pcie-ep"; power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ <0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ reg-names = "appl", "atu_dma", "dbi", "addr_space"; interrupts = ; /* controller interrupt */ interrupt-names = "intr"; clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; clock-names = "core"; resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, <&bpmp TEGRA234_RESET_PEX1_CORE_5>; reset-names = "apb", "core"; nvidia,bpmp = <&bpmp 5>; nvidia,enable-ext-refclk; nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; vddio-pex-ctl-supply = <&p3701_vdd_1v8_ls>; reset-gpios = <&gpio TEGRA234_MAIN_GPIO(AF, 1) GPIO_ACTIVE_LOW>; nvidia,refclk-select-gpios = <&gpio_aon TEGRA234_AON_GPIO(AA, 4) GPIO_ACTIVE_HIGH>; num-lanes = <8>; phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, <&p2u_nvhs_6>, <&p2u_nvhs_7>; phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", "p2u-5", "p2u-6", "p2u-7"; }; };