# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/mtd/nvidia,tegra20-nand.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: NVIDIA Tegra NAND Flash Controller maintainers: - Jonathan Hunter allOf: - $ref: nand-controller.yaml description: The NVIDIA NAND controller provides an interface between NVIDIA SoCs and raw NAND flash devices. It supports standard NAND operations, hardware-assisted ECC, OOB data access, and DMA transfers, and integrates with the Linux MTD NAND subsystem for reliable flash management. properties: compatible: const: nvidia,tegra20-nand reg: maxItems: 1 interrupts: maxItems: 1 clocks: maxItems: 1 clock-names: items: - const: nand resets: maxItems: 1 reset-names: items: - const: nand power-domains: maxItems: 1 operating-points-v2: maxItems: 1 patternProperties: '^nand@': type: object description: Individual NAND chip connected to the NAND controller $ref: raw-nand-chip.yaml# properties: reg: maximum: 5 unevaluatedProperties: false required: - compatible - reg - interrupts - clocks - clock-names - resets - reset-names unevaluatedProperties: false examples: - | #include #include #include nand-controller@70008000 { compatible = "nvidia,tegra20-nand"; reg = <0x70008000 0x100>; interrupts = ; clocks = <&tegra_car TEGRA20_CLK_NDFLASH>; clock-names = "nand"; resets = <&tegra_car 13>; reset-names = "nand"; #address-cells = <1>; #size-cells = <0>; nand@0 { reg = <0>; #address-cells = <1>; #size-cells = <1>; nand-bus-width = <8>; nand-on-flash-bbt; nand-ecc-algo = "bch"; nand-ecc-strength = <8>; wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>; }; }; ...