# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/memory-controllers/renesas,rzg3e-xspi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Renesas Expanded Serial Peripheral Interface (xSPI) maintainers: - Biju Das description: | Renesas xSPI allows a SPI flash connected to the SoC to be accessed via the memory-mapping or the manual command mode. The flash chip itself should be represented by a subnode of the XSPI node. The flash interface is selected based on the "compatible" property of this subnode: - "jedec,spi-nor"; allOf: - $ref: /schemas/spi/spi-controller.yaml# properties: compatible: const: renesas,r9a09g047-xspi # RZ/G3E reg: items: - description: xSPI registers - description: direct mapping area reg-names: items: - const: regs - const: dirmap interrupts: items: - description: Interrupt pulse signal by factors excluding errors - description: Interrupt pulse signal by error factors interrupt-names: items: - const: pulse - const: err_pulse clocks: items: - description: AHB clock - description: AXI clock - description: SPI clock - description: Double speed SPI clock clock-names: items: - const: ahb - const: axi - const: spi - const: spix2 power-domains: maxItems: 1 resets: items: - description: Hardware reset - description: AXI reset reset-names: items: - const: hresetn - const: aresetn renesas,xspi-cs-addr-sys: $ref: /schemas/types.yaml#/definitions/phandle description: | Phandle to the system controller (sys) that allows to configure xSPI CS0 and CS1 addresses. patternProperties: "flash@[0-9a-f]+$": type: object additionalProperties: true properties: compatible: contains: const: jedec,spi-nor required: - compatible - reg - reg-names - interrupts - interrupt-names - clocks - clock-names - power-domains - resets - reset-names - '#address-cells' - '#size-cells' unevaluatedProperties: false examples: - | #include #include spi@11030000 { compatible = "renesas,r9a09g047-xspi"; reg = <0x11030000 0x10000>, <0x20000000 0x10000000>; reg-names = "regs", "dirmap"; interrupts = , ; interrupt-names = "pulse", "err_pulse"; clocks = <&cpg CPG_MOD 0x9f>, <&cpg CPG_MOD 0xa0>, <&cpg CPG_CORE 9>, <&cpg CPG_MOD 0xa1>; clock-names = "ahb", "axi", "spi", "spix2"; power-domains = <&cpg>; resets = <&cpg 0xa3>, <&cpg 0xa4>; reset-names = "hresetn", "aresetn"; #address-cells = <1>; #size-cells = <0>; flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <40000000>; spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; }; };