# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/media/rockchip,rk3568-mipi-csi2.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Rockchip MIPI CSI-2 Receiver maintainers: - Michael Riesch description: The Rockchip MIPI CSI-2 Receiver is a CSI-2 bridge with one input port and one output port. It receives the data with the help of an external MIPI PHY (C-PHY or D-PHY) and passes it to the Rockchip Video Capture (VICAP) block. properties: compatible: enum: - fsl,imx93-mipi-csi2 - rockchip,rk3568-mipi-csi2 reg: maxItems: 1 interrupts: items: - description: Interrupt that signals changes in CSI2HOST_ERR1. - description: Interrupt that signals changes in CSI2HOST_ERR2. minItems: 1 interrupt-names: items: - const: err1 - const: err2 minItems: 1 clocks: minItems: 1 maxItems: 2 clock-names: items: - const: per - const: pixel minItems: 1 phys: maxItems: 1 description: MIPI C-PHY or D-PHY. ports: $ref: /schemas/graph.yaml#/properties/ports properties: port@0: $ref: /schemas/graph.yaml#/$defs/port-base unevaluatedProperties: false description: Input port node. Connect to e.g., a MIPI CSI-2 image sensor. properties: endpoint: $ref: video-interfaces.yaml# unevaluatedProperties: false properties: bus-type: enum: - 1 # MEDIA_BUS_TYPE_CSI2_CPHY - 4 # MEDIA_BUS_TYPE_CSI2_DPHY data-lanes: minItems: 1 maxItems: 4 required: - bus-type - data-lanes port@1: $ref: /schemas/graph.yaml#/properties/port description: Output port connected to a Rockchip VICAP port. required: - port@0 - port@1 power-domains: maxItems: 1 resets: maxItems: 1 required: - compatible - reg - clocks - phys - ports - power-domains additionalProperties: false allOf: - if: properties: compatible: contains: const: rockchip,rk3568-mipi-csi2 then: properties: interrupts: minItems: 2 interrupt-names: minItems: 2 clocks: maxItems: 1 clock-names: maxItems: 1 required: - resets - if: properties: compatible: contains: const: fsl,imx93-mipi-csi2 then: properties: interrupts: maxItems: 1 interrupt-names: false clocks: minItems: 2 clock-names: minItems: 2 examples: - | #include #include #include #include soc { interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; csi: csi@fdfb0000 { compatible = "rockchip,rk3568-mipi-csi2"; reg = <0x0 0xfdfb0000 0x0 0x10000>; interrupts = , ; interrupt-names = "err1", "err2"; clocks = <&cru PCLK_CSI2HOST1>; phys = <&csi_dphy>; power-domains = <&power RK3568_PD_VI>; resets = <&cru SRST_P_CSI2HOST1>; ports { #address-cells = <1>; #size-cells = <0>; csi_in: port@0 { reg = <0>; csi_input: endpoint { bus-type = ; data-lanes = <1 2 3 4>; remote-endpoint = <&imx415_output>; }; }; csi_out: port@1 { reg = <1>; csi_output: endpoint { remote-endpoint = <&vicap_mipi_input>; }; }; }; }; };