# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/media/qcom,qcs8300-camss.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm QCS8300 CAMSS ISP maintainers: - Vikram Sharma description: The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. properties: compatible: const: qcom,qcs8300-camss reg: maxItems: 21 reg-names: items: - const: csid_wrapper - const: csid0 - const: csid1 - const: csid_lite0 - const: csid_lite1 - const: csid_lite2 - const: csid_lite3 - const: csid_lite4 - const: csiphy0 - const: csiphy1 - const: csiphy2 - const: tpg0 - const: tpg1 - const: tpg2 - const: vfe0 - const: vfe1 - const: vfe_lite0 - const: vfe_lite1 - const: vfe_lite2 - const: vfe_lite3 - const: vfe_lite4 clocks: maxItems: 26 clock-names: items: - const: camnoc_axi - const: core_ahb - const: cpas_ahb - const: cpas_fast_ahb_clk - const: cpas_vfe_lite - const: cpas_vfe0 - const: cpas_vfe1 - const: csid - const: csiphy0 - const: csiphy0_timer - const: csiphy1 - const: csiphy1_timer - const: csiphy2 - const: csiphy2_timer - const: csiphy_rx - const: gcc_axi_hf - const: gcc_axi_sf - const: icp_ahb - const: vfe0 - const: vfe0_fast_ahb - const: vfe1 - const: vfe1_fast_ahb - const: vfe_lite - const: vfe_lite_ahb - const: vfe_lite_cphy_rx - const: vfe_lite_csid interrupts: maxItems: 20 interrupt-names: items: - const: csid0 - const: csid1 - const: csid_lite0 - const: csid_lite1 - const: csid_lite2 - const: csid_lite3 - const: csid_lite4 - const: csiphy0 - const: csiphy1 - const: csiphy2 - const: tpg0 - const: tpg1 - const: tpg2 - const: vfe0 - const: vfe1 - const: vfe_lite0 - const: vfe_lite1 - const: vfe_lite2 - const: vfe_lite3 - const: vfe_lite4 interconnects: maxItems: 2 interconnect-names: items: - const: ahb - const: hf_0 iommus: maxItems: 1 power-domains: items: - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller. power-domain-names: items: - const: top ports: $ref: /schemas/graph.yaml#/properties/ports description: CSI input ports. patternProperties: "^port@[0-2]+$": $ref: /schemas/graph.yaml#/$defs/port-base unevaluatedProperties: false description: Input port for receiving CSI data on CSIPHY 0-2. properties: endpoint: $ref: video-interfaces.yaml# unevaluatedProperties: false properties: data-lanes: minItems: 1 maxItems: 4 required: - data-lanes required: - compatible - reg - reg-names - clocks - clock-names - interrupts - interrupt-names - interconnects - interconnect-names - iommus - power-domains - power-domain-names - ports additionalProperties: false examples: - | #include #include #include #include #include #include soc { #address-cells = <2>; #size-cells = <2>; isp@ac78000 { compatible = "qcom,qcs8300-camss"; reg = <0x0 0xac78000 0x0 0x1000>, <0x0 0xac7a000 0x0 0x0f00>, <0x0 0xac7c000 0x0 0x0f00>, <0x0 0xac84000 0x0 0x0f00>, <0x0 0xac88000 0x0 0x0f00>, <0x0 0xac8c000 0x0 0x0f00>, <0x0 0xac90000 0x0 0x0f00>, <0x0 0xac94000 0x0 0x0f00>, <0x0 0xac9c000 0x0 0x2000>, <0x0 0xac9e000 0x0 0x2000>, <0x0 0xaca0000 0x0 0x2000>, <0x0 0xacac000 0x0 0x0400>, <0x0 0xacad000 0x0 0x0400>, <0x0 0xacae000 0x0 0x0400>, <0x0 0xac4d000 0x0 0xd000>, <0x0 0xac60000 0x0 0xd000>, <0x0 0xac85000 0x0 0x0d00>, <0x0 0xac89000 0x0 0x0d00>, <0x0 0xac8d000 0x0 0x0d00>, <0x0 0xac91000 0x0 0x0d00>, <0x0 0xac95000 0x0 0x0d00>; reg-names = "csid_wrapper", "csid0", "csid1", "csid_lite0", "csid_lite1", "csid_lite2", "csid_lite3", "csid_lite4", "csiphy0", "csiphy1", "csiphy2", "tpg0", "tpg1", "tpg2", "vfe0", "vfe1", "vfe_lite0", "vfe_lite1", "vfe_lite2", "vfe_lite3", "vfe_lite4"; clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, <&camcc CAM_CC_CORE_AHB_CLK>, <&camcc CAM_CC_CPAS_AHB_CLK>, <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, <&camcc CAM_CC_CPAS_IFE_0_CLK>, <&camcc CAM_CC_CPAS_IFE_1_CLK>, <&camcc CAM_CC_CSID_CLK>, <&camcc CAM_CC_CSIPHY0_CLK>, <&camcc CAM_CC_CSI0PHYTIMER_CLK>, <&camcc CAM_CC_CSIPHY1_CLK>, <&camcc CAM_CC_CSI1PHYTIMER_CLK>, <&camcc CAM_CC_CSIPHY2_CLK>, <&camcc CAM_CC_CSI2PHYTIMER_CLK>, <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, <&gcc GCC_CAMERA_HF_AXI_CLK>, <&gcc GCC_CAMERA_SF_AXI_CLK>, <&camcc CAM_CC_ICP_AHB_CLK>, <&camcc CAM_CC_IFE_0_CLK>, <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, <&camcc CAM_CC_IFE_1_CLK>, <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, <&camcc CAM_CC_IFE_LITE_CLK>, <&camcc CAM_CC_IFE_LITE_AHB_CLK>, <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, <&camcc CAM_CC_IFE_LITE_CSID_CLK>; clock-names = "camnoc_axi", "core_ahb", "cpas_ahb", "cpas_fast_ahb_clk", "cpas_vfe_lite", "cpas_vfe0", "cpas_vfe1", "csid", "csiphy0", "csiphy0_timer", "csiphy1", "csiphy1_timer", "csiphy2", "csiphy2_timer", "csiphy_rx", "gcc_axi_hf", "gcc_axi_sf", "icp_ahb", "vfe0", "vfe0_fast_ahb", "vfe1", "vfe1_fast_ahb", "vfe_lite", "vfe_lite_ahb", "vfe_lite_cphy_rx", "vfe_lite_csid"; interrupts = , , , , , , , , , , , , , , , , , , , ; interrupt-names = "csid0", "csid1", "csid_lite0", "csid_lite1", "csid_lite2", "csid_lite3", "csid_lite4", "csiphy0", "csiphy1", "csiphy2", "tpg0", "tpg1", "tpg2", "vfe0", "vfe1", "vfe_lite0", "vfe_lite1", "vfe_lite2", "vfe_lite3", "vfe_lite4"; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "ahb", "hf_0"; iommus = <&apps_smmu 0x2400 0x20>; power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; power-domain-names = "top"; ports { #address-cells = <1>; #size-cells = <0>; }; }; };