# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/iio/adc/adi,ad4134.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Analog Devices AD4134 ADC maintainers: - Marcelo Schmitt description: | The AD4134 is a quad channel, low noise, simultaneous sampling, precision analog-to-digital converter (ADC). Specifications can be found at: https://www.analog.com/media/en/technical-documentation/data-sheets/ad4134.pdf $ref: /schemas/spi/spi-peripheral-props.yaml# properties: compatible: enum: - adi,ad4134 reg: maxItems: 1 spi-max-frequency: maximum: 50000000 avdd5-supply: description: A 5V supply that powers the chip's analog circuitry. dvdd5-supply: description: A 5V supply that powers the chip's digital circuitry. iovdd-supply: description: A 1.8V supply that sets the logic levels for the digital interface pins. refin-supply: description: A 4.096V or 5V supply that serves as reference for ADC conversions. avdd1v8-supply: description: A 1.8V supply used by the analog circuitry. dvdd1v8-supply: description: A 1.8V supply used by the digital circuitry. clkvdd-supply: description: A 1.8V supply for the chip's clock management circuit. ldoin-supply: description: A 2.6V to 5.5V supply that generates 1.8V for AVDD1V8, DVDD1V8, and CLKVDD pins. clocks: maxItems: 1 description: Required external clock source. Can specify either a crystal or CMOS clock source. If an external crystal is set, connect the CLKSEL pin to IOVDD. Otherwise, connect the CLKSEL pin to IOGND and the external CMOS clock signal to the XTAL2/CLKIN pin. clock-names: enum: - xtal - clkin default: clkin '#clock-cells': const: 0 clock-output-names: maxItems: 1 regulators: type: object description: list of regulators provided by this controller. properties: vcm-output: $ref: /schemas/regulator/regulator.yaml# type: object unevaluatedProperties: false additionalProperties: false reset-gpios: maxItems: 1 powerdown-gpios: description: Active low GPIO connected to the /PDN pin. Forces the device into full power-down mode when brought low. Pull this input to IOVDD for normal operation. maxItems: 1 odr-gpios: description: GPIO connected to ODR pin. Used to sample ADC data in minimum I/O mode. maxItems: 1 adi,asrc-mode: $ref: /schemas/types.yaml#/definitions/string description: Asynchronous Sample Rate Converter (ASRC) operation mode control input. Describes whether the MODE pin is set to a high level (for master mode operation) or to a low level (for slave mode operation). enum: [ high, low ] default: low adi,dclkio: description: DCLK pin I/O direction control for when the device operates in Pin Control Slave Mode or in SPI Control Mode. Describes if DEC0/DCLKIO pin is at a high level (which configures DCLK as an output) or to set to a low level (configuring DCLK for input). enum: [ out, in ] default: in adi,dclkmode: description: DCLK mode control for when the device operates in Pin Control Slave Mode or in SPI Control Mode. Describes whether the DEC1/DCLKMODE pin is set to a high level (configuring the DCLK to operate in free running mode) or to a low level (to configure DCLK to operate in gated mode). enum: [ free-running, gated ] default: gated required: - compatible - reg - avdd5-supply - dvdd5-supply - iovdd-supply - refin-supply - clocks - clock-names oneOf: - required: - ldoin-supply - required: - avdd1v8-supply - dvdd1v8-supply - clkvdd-supply unevaluatedProperties: false examples: - | #include spi { #address-cells = <1>; #size-cells = <0>; adc@0 { compatible = "adi,ad4134"; reg = <0>; spi-max-frequency = <1000000>; reset-gpios = <&gpio0 86 GPIO_ACTIVE_LOW>; odr-gpios = <&gpio0 87 GPIO_ACTIVE_HIGH>; powerdown-gpios = <&gpio0 88 GPIO_ACTIVE_LOW>; clocks = <&sys_clk>; clock-names = "clkin"; avdd5-supply = <&avdd5>; dvdd5-supply = <&dvdd5>; iovdd-supply = <&iovdd>; refin-supply = <&refin>; avdd1v8-supply = <&avdd1v8>; dvdd1v8-supply = <&dvdd1v8>; clkvdd-supply = <&clkvdd>; regulators { vcm_reg: vcm-output { regulator-name = "ad4134-vcm"; }; }; }; }; ...