# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/i3c/xlnx,axi-i3c-1.0.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: AMD I3C master

maintainers:
  - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
  - Shubham Patil <shubhamsanjay.patil@amd.com>

description:
  The AXI-I3C IP is an I3C Controller with an AXI4-Lite interface, compatible
  with the MIPI I3C Specification v1.1.1. The design includes bidirectional I/O
  buffers that implement open collector drivers for the SDA and SCL signals.
  External pull-up resistors are required to properly hold the bus at a Logic-1
  level when the drivers are released.

  For more details, please see https://docs.amd.com/r/en-US/pg439-axi-i3c

properties:
  compatible:
    const: xlnx,axi-i3c-1.0

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  interrupts:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks

allOf:
  - $ref: i3c.yaml#

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    i3c@80000000 {
        compatible = "xlnx,axi-i3c-1.0";
        reg = <0x80000000 0x10000>;
        clocks = <&zynqmp_clk 71>;
        interrupt-parent = <&imux>;
        interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
        #address-cells = <3>;
        #size-cells = <0>;
    };
...