# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/dma/renesas,rz-dmac.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Renesas RZ DMA Controller maintainers: - Biju Das properties: compatible: oneOf: - items: - enum: - renesas,r7s72100-dmac # RZ/A1H - renesas,r9a07g043-dmac # RZ/G2UL and RZ/Five - renesas,r9a07g044-dmac # RZ/G2{L,LC} - renesas,r9a07g054-dmac # RZ/V2L - renesas,r9a08g045-dmac # RZ/G3S - const: renesas,rz-dmac - const: renesas,r9a09g057-dmac # RZ/V2H(P) reg: items: - description: Control and channel register block - description: DMA extended resource selector block minItems: 1 interrupts: maxItems: 17 interrupt-names: items: - const: error - const: ch0 - const: ch1 - const: ch2 - const: ch3 - const: ch4 - const: ch5 - const: ch6 - const: ch7 - const: ch8 - const: ch9 - const: ch10 - const: ch11 - const: ch12 - const: ch13 - const: ch14 - const: ch15 clocks: items: - description: DMA main clock - description: DMA register access clock minItems: 1 clock-names: items: - const: main - const: register '#dma-cells': const: 1 description: The cell specifies the encoded MID/RID or the REQ No values of the DMAC port connected to the DMA client and the slave channel configuration parameters. bits[0:9] - Specifies the MID/RID or the REQ No value bit[10] - Specifies DMA request high enable (HIEN) bit[11] - Specifies DMA request detection type (LVL) bits[12:14] - Specifies DMAACK output mode (AM) bit[15] - Specifies Transfer Mode (TM) dma-channels: const: 16 power-domains: maxItems: 1 resets: items: - description: Reset for DMA ARESETN reset terminal - description: Reset for DMA RST_ASYNC reset terminal minItems: 1 reset-names: items: - const: arst - const: rst_async renesas,icu: description: It must contain the phandle to the ICU and the index of the DMAC as seen from the ICU. $ref: /schemas/types.yaml#/definitions/phandle-array items: - items: - description: Phandle to the ICU node. - description: The number of the DMAC as seen from the ICU, i.e. parameter k from register ICU_DMkSELy. This may differ from the actual DMAC instance number. required: - compatible - reg - interrupts - interrupt-names - '#dma-cells' - dma-channels allOf: - $ref: dma-controller.yaml# - if: properties: compatible: contains: enum: - renesas,r9a07g043-dmac - renesas,r9a07g044-dmac - renesas,r9a07g054-dmac - renesas,r9a08g045-dmac then: properties: reg: minItems: 2 clocks: minItems: 2 resets: minItems: 2 renesas,icu: false required: - clocks - clock-names - power-domains - resets - reset-names - if: properties: compatible: contains: const: renesas,r7s72100-dmac then: properties: reg: minItems: 2 clocks: false clock-names: false power-domains: false resets: false reset-names: false renesas,icu: false - if: properties: compatible: contains: const: renesas,r9a09g057-dmac then: properties: reg: maxItems: 1 clocks: maxItems: 1 resets: maxItems: 1 clock-names: false reset-names: false required: - clocks - power-domains - renesas,icu - resets additionalProperties: false examples: - | #include #include dmac: dma-controller@11820000 { compatible = "renesas,r9a07g044-dmac", "renesas,rz-dmac"; reg = <0x11820000 0x10000>, <0x11830000 0x10000>; interrupts = , , , , , , , , , , , , , , , , ; interrupt-names = "error", "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14", "ch15"; clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>, <&cpg CPG_MOD R9A07G044_DMAC_PCLK>; clock-names = "main", "register"; power-domains = <&cpg>; resets = <&cpg R9A07G044_DMAC_ARESETN>, <&cpg R9A07G044_DMAC_RST_ASYNC>; reset-names = "arst", "rst_async"; #dma-cells = <1>; dma-channels = <16>; };