# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/qcom,milos-mdss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Milos Display MDSS

maintainers:
  - Luca Weiss <luca.weiss@fairphone.com>

description:
  Milos MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
  DPU display controller, DSI and DP interfaces etc.

$ref: /schemas/display/msm/mdss-common.yaml#

properties:
  compatible:
    const: qcom,milos-mdss

  clocks:
    items:
      - description: Display AHB
      - description: Display hf AXI
      - description: Display core

  iommus:
    maxItems: 1

  interconnects:
    items:
      - description: Interconnect path from mdp0 port to the data bus
      - description: Interconnect path from CPU to the reg bus

  interconnect-names:
    items:
      - const: mdp0-mem
      - const: cpu-cfg

patternProperties:
  "^display-controller@[0-9a-f]+$":
    type: object
    additionalProperties: true
    properties:
      compatible:
        const: qcom,milos-dpu

  "^displayport-controller@[0-9a-f]+$":
    type: object
    additionalProperties: true
    properties:
      compatible:
        const: qcom,milos-dp

  "^dsi@[0-9a-f]+$":
    type: object
    additionalProperties: true
    properties:
      compatible:
        contains:
          const: qcom,milos-dsi-ctrl

  "^phy@[0-9a-f]+$":
    type: object
    additionalProperties: true
    properties:
      compatible:
        const: qcom,milos-dsi-phy-4nm

required:
  - compatible

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
    #include <dt-bindings/clock/qcom,milos-dispcc.h>
    #include <dt-bindings/clock/qcom,milos-gcc.h>
    #include <dt-bindings/clock/qcom,rpmh.h>
    #include <dt-bindings/interconnect/qcom,icc.h>
    #include <dt-bindings/interconnect/qcom,milos-rpmh.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/qcom,rpmhpd.h>

    display-subsystem@ae00000 {
        compatible = "qcom,milos-mdss";
        reg = <0x0ae00000 0x1000>;
        reg-names = "mdss";

        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH 0>;

        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
                 <&gcc GCC_DISP_HF_AXI_CLK>,
                 <&dispcc DISP_CC_MDSS_MDP_CLK>;

        resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;

        interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS
                         &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
                        <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
                         &cnoc_main SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
        interconnect-names = "mdp0-mem",
                             "cpu-cfg";

        power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;

        iommus = <&apps_smmu 0x1c00 0x2>;

        interrupt-controller;
        #interrupt-cells = <1>;

        #address-cells = <1>;
        #size-cells = <1>;
        ranges;

        display-controller@ae01000 {
            compatible = "qcom,milos-dpu";
            reg = <0x0ae01000 0x8f000>,
                  <0x0aeb0000 0x3000>;
            reg-names = "mdp",
                        "vbif";

            interrupts-extended = <&mdss 0>;

            clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
                     <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
                     <&dispcc DISP_CC_MDSS_MDP_CLK>,
                     <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
            clock-names = "nrt_bus",
                          "iface",
                          "lut",
                          "core",
                          "vsync";

            assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
            assigned-clock-rates = <19200000>;

            operating-points-v2 = <&mdp_opp_table>;

            power-domains = <&rpmhpd RPMHPD_CX>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;

                    dpu_intf1_out: endpoint {
                        remote-endpoint = <&mdss_dsi0_in>;
                    };
                };
            };

            mdp_opp_table: opp-table {
                compatible = "operating-points-v2";

                opp-200000000 {
                    opp-hz = /bits/ 64 <200000000>;
                    required-opps = <&rpmhpd_opp_low_svs>;
                };

                opp-342000000 {
                    opp-hz = /bits/ 64 <342000000>;
                    required-opps = <&rpmhpd_opp_svs>;
                };

                opp-402000000 {
                    opp-hz = /bits/ 64 <402000000>;
                    required-opps = <&rpmhpd_opp_svs_l1>;
                };

                opp-535000000 {
                    opp-hz = /bits/ 64 <535000000>;
                    required-opps = <&rpmhpd_opp_nom>;
                };

                opp-600000000 {
                    opp-hz = /bits/ 64 <600000000>;
                    required-opps = <&rpmhpd_opp_nom_l1>;
                };

                opp-630000000 {
                    opp-hz = /bits/ 64 <630000000>;
                    required-opps = <&rpmhpd_opp_turbo>;
                };
            };
        };

        dsi@ae94000 {
            compatible = "qcom,milos-dsi-ctrl", "qcom,mdss-dsi-ctrl";
            reg = <0x0ae94000 0x1000>;
            reg-names = "dsi_ctrl";

            interrupts-extended = <&mdss 4>;

            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
                     <&gcc GCC_DISP_HF_AXI_CLK>;
            clock-names = "byte",
                          "byte_intf",
                          "pixel",
                          "core",
                          "iface",
                          "bus";

            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
                              <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
            assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
                                     <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>;

            operating-points-v2 = <&mdss_dsi_opp_table>;

            power-domains = <&rpmhpd RPMHPD_CX>;

            phys = <&mdss_dsi0_phy>;
            phy-names = "dsi";

            #address-cells = <1>;
            #size-cells = <0>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;

                    mdss_dsi0_in: endpoint {
                        remote-endpoint = <&dpu_intf1_out>;
                    };
                };

                port@1 {
                    reg = <1>;

                    mdss_dsi0_out: endpoint {
                    };
                };
            };

            mdss_dsi_opp_table: opp-table {
                compatible = "operating-points-v2";

                opp-187500000 {
                    opp-hz = /bits/ 64 <187500000>;
                    required-opps = <&rpmhpd_opp_low_svs>;
                };

                opp-300000000 {
                    opp-hz = /bits/ 64 <300000000>;
                    required-opps = <&rpmhpd_opp_svs>;
                };

                opp-358000000 {
                    opp-hz = /bits/ 64 <358000000>;
                    required-opps = <&rpmhpd_opp_svs_l1>;
                };
            };
        };

        mdss_dsi0_phy: phy@ae95000 {
            compatible = "qcom,milos-dsi-phy-4nm";
            reg = <0x0ae95000 0x200>,
                  <0x0ae95200 0x300>,
                  <0x0ae95500 0x400>;
            reg-names = "dsi_phy",
                        "dsi_phy_lane",
                        "dsi_pll";

            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
                     <&rpmhcc RPMH_CXO_CLK>;
            clock-names = "iface",
                          "ref";

            #clock-cells = <1>;
            #phy-cells = <0>;
        };
    };
...