# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx53-tve.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale i.MX53 Television Encoder (TVE)

maintainers:
  - Frank Li <Frank.Li@nxp.com>

description:
  The Television Encoder (TVE) is a hardware block in the i.MX53 SoC that
  converts digital video data into analog TV signals (NTSC/PAL).

properties:
  compatible:
    const: fsl,imx53-tve

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: TVE gate clock
      - description: Display interface selector clock

  clock-names:
    items:
      - const: tve
      - const: di_sel

  ddc-i2c-bus:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to the I2C bus used for DDC (Display Data Channel) communication
      to read EDID information from the connected display.

  dac-supply:
    description:
      Regulator supply for the TVE DAC (Digital-to-Analog Converter).

  fsl,tve-mode:
    $ref: /schemas/types.yaml#/definitions/string
    description:
      TVE output mode selection.
    enum:
      - ntsc
      - pal
      - vga

  fsl,hsync-pin:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Pin number for horizontal sync signal in VGA mode.
    minimum: 0
    maximum: 8

  fsl,vsync-pin:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Pin number for vertical sync signal in VGA mode.
    minimum: 0
    maximum: 8

  port:
    $ref: /schemas/graph.yaml#/properties/port
    description:
      Port node with one endpoint connected to the IPU display interface.

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - fsl,tve-mode

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx5-clock.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    tve@63ff0000 {
        compatible = "fsl,imx53-tve";
        reg = <0x63ff0000 0x1000>;
        interrupts = <92>;
        clocks = <&clks IMX5_CLK_TVE_GATE>,
                 <&clks IMX5_CLK_IPU_DI1_SEL>;
        clock-names = "tve", "di_sel";
        fsl,tve-mode = "vga";

        port {
            endpoint {
                remote-endpoint = <&ipu_di1_tve>;
            };
        };
    };