From c7bd3e07be41cd1e094528a7cba9b316d15c6844 Mon Sep 17 00:00:00 2001 From: Joakim Tjernlund Date: Mon, 10 Oct 2011 13:30:19 +0200 Subject: 8xx: Optimize TLB Miss handlers Only update pte w.r.t ACCESSED if it isn't already set Wrap ACCESSED with #ifndef NO_SWAP for too ease optimization. Signed-off-by: Joakim Tjernlund Signed-off-by: Willy Tarreau --- arch/ppc/kernel/head_8xx.S | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S index 0f2101d1e4cea..36089cccf0862 100644 --- a/arch/ppc/kernel/head_8xx.S +++ b/arch/ppc/kernel/head_8xx.S @@ -377,10 +377,14 @@ InstructionTLBMiss: mfspr r21, MD_TWC /* ....and get the pte address */ lwz r20, 0(r21) /* Get the pte */ -#if 1 +#ifndef NO_SWAP /* if !swap, you can delete this */ + andi. r21, r20, _PAGE_ACCESSED /* test ACCESSED bit */ + bne+ 4f /* Branch if set */ + mfspr r21, MD_TWC /* get the pte address */ rlwimi r20, r20, 5, _PAGE_PRESENT<<5 /* Copy PRESENT to ACCESSED */ stw r20, 0(r21) /* Update pte */ +4: #endif /* The Linux PTE won't go exactly into the MMU TLB. * Software indicator bits 21 and 28 must be clear. @@ -450,11 +454,14 @@ DataStoreTLBMiss: DO_8xx_CPU6(0x3b80, r3) mtspr MD_TWC, r21 -#if 1 +#ifndef NO_SWAP /* if !swap, you can delete this */ + andi. r21, r20, _PAGE_ACCESSED /* test ACCESSED bit */ + bne+ 4f /* Branch if set */ mfspr r21, MD_TWC /* get the pte address */ rlwimi r20, r20, 5, _PAGE_PRESENT<<5 /* Copy PRESENT to ACCESSED */ stw r20, 0(r21) /* Update pte */ +4: #endif /* Honour kernel RO, User NA */ -- cgit 1.2.3-korg