From 192ef366198ce16c0379100565cdc5b7bd68511f Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Fri, 7 Jul 2006 14:07:18 +0100 Subject: [MIPS] TRACE_IRQFLAGS_SUPPORT support. Signed-off-by: Ralf Baechle --- arch/mips/Kconfig.debug | 4 + arch/mips/kernel/entry.S | 15 +++ arch/mips/kernel/gdb-low.S | 2 + arch/mips/kernel/genex.S | 6 ++ arch/mips/kernel/head.S | 3 +- arch/mips/kernel/scall32-o32.S | 15 ++- arch/mips/kernel/scall64-64.S | 2 + arch/mips/kernel/scall64-n32.S | 2 + arch/mips/kernel/scall64-o32.S | 2 + arch/mips/kernel/smtc-asm.S | 1 + include/asm-mips/atomic.h | 2 +- include/asm-mips/bitops.h | 2 +- include/asm-mips/interrupt.h | 221 ---------------------------------------- include/asm-mips/irqflags.h | 225 +++++++++++++++++++++++++++++++++++++++++ include/asm-mips/mipsregs.h | 2 +- include/asm-mips/system.h | 2 +- 16 files changed, 279 insertions(+), 227 deletions(-) delete mode 100644 include/asm-mips/interrupt.h create mode 100644 include/asm-mips/irqflags.h diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug index 515f9e6113074..5d6afb52d904a 100644 --- a/arch/mips/Kconfig.debug +++ b/arch/mips/Kconfig.debug @@ -1,5 +1,9 @@ menu "Kernel hacking" +config TRACE_IRQFLAGS_SUPPORT + bool + default y + source "lib/Kconfig.debug" config CROSSCOMPILE diff --git a/arch/mips/kernel/entry.S b/arch/mips/kernel/entry.S index 01e7fa86aa43d..766655f352508 100644 --- a/arch/mips/kernel/entry.S +++ b/arch/mips/kernel/entry.S @@ -113,6 +113,21 @@ FEXPORT(restore_all) # restore full frame RESTORE_AT RESTORE_STATIC FEXPORT(restore_partial) # restore partial frame +#ifdef CONFIG_TRACE_IRQFLAGS + SAVE_STATIC + SAVE_AT + SAVE_TEMP + LONG_L v0, PT_STATUS(sp) + and v0, 1 + beqz v0, 1f + jal trace_hardirqs_on + b 2f +1: jal trace_hardirqs_off +2: + RESTORE_TEMP + RESTORE_AT + RESTORE_STATIC +#endif RESTORE_SOME RESTORE_SP_AND_RET .set at diff --git a/arch/mips/kernel/gdb-low.S b/arch/mips/kernel/gdb-low.S index 666bc9014cbd9..2c446063636ae 100644 --- a/arch/mips/kernel/gdb-low.S +++ b/arch/mips/kernel/gdb-low.S @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -120,6 +121,7 @@ LONG_S $31, GDB_FR_REG31(sp) CLI /* disable interrupts */ + TRACE_IRQS_OFF /* * Followed by the floating point registers diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S index b563811b1b270..37fda3dcdfc5b 100644 --- a/arch/mips/kernel/genex.S +++ b/arch/mips/kernel/genex.S @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -128,6 +129,7 @@ handle_vcei: NESTED(handle_int, PT_SIZE, sp) SAVE_ALL CLI + TRACE_IRQS_OFF PTR_LA ra, ret_from_irq move a0, sp @@ -216,6 +218,7 @@ NESTED(except_vec_vi_handler, 0, sp) _ehb #endif /* CONFIG_MIPS_MT_SMTC */ CLI + TRACE_IRQS_OFF move a0, sp jalr v0 j ret_from_irq @@ -288,11 +291,13 @@ NESTED(nmi_handler, PT_SIZE, sp) .endm .macro __build_clear_sti + TRACE_IRQS_ON STI .endm .macro __build_clear_cli CLI + TRACE_IRQS_OFF .endm .macro __build_clear_fpe @@ -300,6 +305,7 @@ NESTED(nmi_handler, PT_SIZE, sp) li a2, ~(0x3f << 12) and a2, a1 ctc1 a2, fcr31 + TRACE_IRQS_ON STI .endm diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S index 476c1eb33c945..8c6db0fc72f0a 100644 --- a/arch/mips/kernel/head.S +++ b/arch/mips/kernel/head.S @@ -5,7 +5,7 @@ * * Copyright (C) 1994, 1995 Waldorf Electronics * Written by Ralf Baechle and Andreas Busse - * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003 Ralf Baechle + * Copyright (C) 1994 - 99, 2003, 06 Ralf Baechle * Copyright (C) 1996 Paul M. Antoine * Modified for DECStation and hence R3000 support by Paul M. Antoine * Further modifications by David S. Miller and Harald Koerfgen @@ -18,6 +18,7 @@ #include #include +#include #include #include #include diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S index c8e5f9c9a1131..ba1bcd83c7d3e 100644 --- a/arch/mips/kernel/scall32-o32.S +++ b/arch/mips/kernel/scall32-o32.S @@ -3,13 +3,14 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1995, 96, 97, 98, 99, 2000, 01, 02 by Ralf Baechle + * Copyright (C) 1995-99, 2000- 02, 06 Ralf Baechle * Copyright (C) 2001 MIPS Technologies, Inc. * Copyright (C) 2004 Thiemo Seufer */ #include #include #include +#include #include #include #include @@ -27,6 +28,18 @@ NESTED(handle_sys, PT_SIZE, sp) .set noat SAVE_SOME +#ifdef CONFIG_TRACE_IRQFLAGS + TRACE_IRQS_ON +#ifdef CONFIG_64BIT + LONG_L $8, PT_R8(sp) + LONG_L $9, PT_R9(sp) +#endif + LONG_L $7, PT_R7(sp) + LONG_L $6, PT_R6(sp) + LONG_L $5, PT_R5(sp) + LONG_L $4, PT_R4(sp) + LONG_L $2, PT_R2(sp) +#endif STI .set at diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S index 809fd1b55f848..939e172db9531 100644 --- a/arch/mips/kernel/scall64-64.S +++ b/arch/mips/kernel/scall64-64.S @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -33,6 +34,7 @@ NESTED(handle_sys64, PT_SIZE, sp) */ .set noat SAVE_SOME + TRACE_IRQS_ON STI .set at #endif diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S index b2b5cb9fe571b..98abbc5a9f130 100644 --- a/arch/mips/kernel/scall64-n32.S +++ b/arch/mips/kernel/scall64-n32.S @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -32,6 +33,7 @@ NESTED(handle_sysn32, PT_SIZE, sp) #ifndef CONFIG_MIPS32_O32 .set noat SAVE_SOME + TRACE_IRQS_ON STI .set at #endif diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S index 3a138dcc88279..505c9ee540095 100644 --- a/arch/mips/kernel/scall64-o32.S +++ b/arch/mips/kernel/scall64-o32.S @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -27,6 +28,7 @@ NESTED(handle_sys, PT_SIZE, sp) .set noat SAVE_SOME + TRACE_IRQS_ON STI .set at ld t1, PT_EPC(sp) # skip syscall on return diff --git a/arch/mips/kernel/smtc-asm.S b/arch/mips/kernel/smtc-asm.S index 72c6d98f88542..4cc3dea366125 100644 --- a/arch/mips/kernel/smtc-asm.S +++ b/arch/mips/kernel/smtc-asm.S @@ -96,6 +96,7 @@ FEXPORT(__smtc_ipi_vector) /* Save all will redundantly recompute the SP, but use it for now */ SAVE_ALL CLI + TRACE_IRQS_OFF move a0,sp /* Function to be invoked passed stack pad slot 5 */ lw t0,PT_PADSLOT5(sp) diff --git a/include/asm-mips/atomic.h b/include/asm-mips/atomic.h index 13d44e14025ac..e64abc0d82217 100644 --- a/include/asm-mips/atomic.h +++ b/include/asm-mips/atomic.h @@ -22,8 +22,8 @@ #ifndef _ASM_ATOMIC_H #define _ASM_ATOMIC_H +#include #include -#include #include typedef struct { volatile int counter; } atomic_t; diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h index 098cec263681b..1bb89c5a10ee6 100644 --- a/include/asm-mips/bitops.h +++ b/include/asm-mips/bitops.h @@ -31,7 +31,7 @@ #ifdef __KERNEL__ -#include +#include #include #include diff --git a/include/asm-mips/interrupt.h b/include/asm-mips/interrupt.h deleted file mode 100644 index a99d6867510fd..0000000000000 --- a/include/asm-mips/interrupt.h +++ /dev/null @@ -1,221 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003 by Ralf Baechle - * Copyright (C) 1996 by Paul M. Antoine - * Copyright (C) 1999 Silicon Graphics - * Copyright (C) 2000 MIPS Technologies, Inc. - */ -#ifndef _ASM_INTERRUPT_H -#define _ASM_INTERRUPT_H - -#include - -__asm__ ( - " .macro local_irq_enable \n" - " .set push \n" - " .set reorder \n" - " .set noat \n" -#ifdef CONFIG_MIPS_MT_SMTC - " mfc0 $1, $2, 1 # SMTC - clear TCStatus.IXMT \n" - " ori $1, 0x400 \n" - " xori $1, 0x400 \n" - " mtc0 $1, $2, 1 \n" -#elif defined(CONFIG_CPU_MIPSR2) - " ei \n" -#else - " mfc0 $1,$12 \n" - " ori $1,0x1f \n" - " xori $1,0x1e \n" - " mtc0 $1,$12 \n" -#endif - " irq_enable_hazard \n" - " .set pop \n" - " .endm"); - -static inline void local_irq_enable(void) -{ - __asm__ __volatile__( - "local_irq_enable" - : /* no outputs */ - : /* no inputs */ - : "memory"); -} - -/* - * For cli() we have to insert nops to make sure that the new value - * has actually arrived in the status register before the end of this - * macro. - * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs - * no nops at all. - */ -/* - * For TX49, operating only IE bit is not enough. - * - * If mfc0 $12 follows store and the mfc0 is last instruction of a - * page and fetching the next instruction causes TLB miss, the result - * of the mfc0 might wrongly contain EXL bit. - * - * ERT-TX49H2-027, ERT-TX49H3-012, ERT-TX49HL3-006, ERT-TX49H4-008 - * - * Workaround: mask EXL bit of the result or place a nop before mfc0. - */ -__asm__ ( - " .macro local_irq_disable\n" - " .set push \n" - " .set noat \n" -#ifdef CONFIG_MIPS_MT_SMTC - " mfc0 $1, $2, 1 \n" - " ori $1, 0x400 \n" - " .set noreorder \n" - " mtc0 $1, $2, 1 \n" -#elif defined(CONFIG_CPU_MIPSR2) - " di \n" -#else - " mfc0 $1,$12 \n" - " ori $1,0x1f \n" - " xori $1,0x1f \n" - " .set noreorder \n" - " mtc0 $1,$12 \n" -#endif - " irq_disable_hazard \n" - " .set pop \n" - " .endm \n"); - -static inline void local_irq_disable(void) -{ - __asm__ __volatile__( - "local_irq_disable" - : /* no outputs */ - : /* no inputs */ - : "memory"); -} - -__asm__ ( - " .macro local_save_flags flags \n" - " .set push \n" - " .set reorder \n" -#ifdef CONFIG_MIPS_MT_SMTC - " mfc0 \\flags, $2, 1 \n" -#else - " mfc0 \\flags, $12 \n" -#endif - " .set pop \n" - " .endm \n"); - -#define local_save_flags(x) \ -__asm__ __volatile__( \ - "local_save_flags %0" \ - : "=r" (x)) - -__asm__ ( - " .macro local_irq_save result \n" - " .set push \n" - " .set reorder \n" - " .set noat \n" -#ifdef CONFIG_MIPS_MT_SMTC - " mfc0 \\result, $2, 1 \n" - " ori $1, \\result, 0x400 \n" - " .set noreorder \n" - " mtc0 $1, $2, 1 \n" - " andi \\result, \\result, 0x400 \n" -#elif defined(CONFIG_CPU_MIPSR2) - " di \\result \n" - " andi \\result, 1 \n" -#else - " mfc0 \\result, $12 \n" - " ori $1, \\result, 0x1f \n" - " xori $1, 0x1f \n" - " .set noreorder \n" - " mtc0 $1, $12 \n" -#endif - " irq_disable_hazard \n" - " .set pop \n" - " .endm \n"); - -#define local_irq_save(x) \ -__asm__ __volatile__( \ - "local_irq_save\t%0" \ - : "=r" (x) \ - : /* no inputs */ \ - : "memory") - -__asm__ ( - " .macro local_irq_restore flags \n" - " .set push \n" - " .set noreorder \n" - " .set noat \n" -#ifdef CONFIG_MIPS_MT_SMTC - "mfc0 $1, $2, 1 \n" - "andi \\flags, 0x400 \n" - "ori $1, 0x400 \n" - "xori $1, 0x400 \n" - "or \\flags, $1 \n" - "mtc0 \\flags, $2, 1 \n" -#elif defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU) - /* - * Slow, but doesn't suffer from a relativly unlikely race - * condition we're having since days 1. - */ - " beqz \\flags, 1f \n" - " di \n" - " ei \n" - "1: \n" -#elif defined(CONFIG_CPU_MIPSR2) - /* - * Fast, dangerous. Life is fun, life is good. - */ - " mfc0 $1, $12 \n" - " ins $1, \\flags, 0, 1 \n" - " mtc0 $1, $12 \n" -#else - " mfc0 $1, $12 \n" - " andi \\flags, 1 \n" - " ori $1, 0x1f \n" - " xori $1, 0x1f \n" - " or \\flags, $1 \n" - " mtc0 \\flags, $12 \n" -#endif - " irq_disable_hazard \n" - " .set pop \n" - " .endm \n"); - -#define local_irq_restore(flags) \ -do { \ - unsigned long __tmp1; \ - \ - __asm__ __volatile__( \ - "local_irq_restore\t%0" \ - : "=r" (__tmp1) \ - : "0" (flags) \ - : "memory"); \ -} while(0) - -static inline int irqs_disabled(void) -{ -#ifdef CONFIG_MIPS_MT_SMTC - /* - * SMTC model uses TCStatus.IXMT to disable interrupts for a thread/CPU - */ - unsigned long __result; - - __asm__ __volatile__( - " .set noreorder \n" - " mfc0 %0, $2, 1 \n" - " andi %0, 0x400 \n" - " slt %0, $0, %0 \n" - " .set reorder \n" - : "=r" (__result)); - - return __result; -#else - unsigned long flags; - local_save_flags(flags); - - return !(flags & 1); -#endif -} - -#endif /* _ASM_INTERRUPT_H */ diff --git a/include/asm-mips/irqflags.h b/include/asm-mips/irqflags.h new file mode 100644 index 0000000000000..43ca09a3a3d0c --- /dev/null +++ b/include/asm-mips/irqflags.h @@ -0,0 +1,225 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003 by Ralf Baechle + * Copyright (C) 1996 by Paul M. Antoine + * Copyright (C) 1999 Silicon Graphics + * Copyright (C) 2000 MIPS Technologies, Inc. + */ +#ifndef _ASM_IRQFLAGS_H +#define _ASM_IRQFLAGS_H + +#ifndef __ASSEMBLY__ + +#include + +__asm__ ( + " .macro raw_local_irq_enable \n" + " .set push \n" + " .set reorder \n" + " .set noat \n" +#ifdef CONFIG_MIPS_MT_SMTC + " mfc0 $1, $2, 1 # SMTC - clear TCStatus.IXMT \n" + " ori $1, 0x400 \n" + " xori $1, 0x400 \n" + " mtc0 $1, $2, 1 \n" +#elif defined(CONFIG_CPU_MIPSR2) + " ei \n" +#else + " mfc0 $1,$12 \n" + " ori $1,0x1f \n" + " xori $1,0x1e \n" + " mtc0 $1,$12 \n" +#endif + " irq_enable_hazard \n" + " .set pop \n" + " .endm"); + +static inline void raw_local_irq_enable(void) +{ + __asm__ __volatile__( + "raw_local_irq_enable" + : /* no outputs */ + : /* no inputs */ + : "memory"); +} + +/* + * For cli() we have to insert nops to make sure that the new value + * has actually arrived in the status register before the end of this + * macro. + * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs + * no nops at all. + */ +/* + * For TX49, operating only IE bit is not enough. + * + * If mfc0 $12 follows store and the mfc0 is last instruction of a + * page and fetching the next instruction causes TLB miss, the result + * of the mfc0 might wrongly contain EXL bit. + * + * ERT-TX49H2-027, ERT-TX49H3-012, ERT-TX49HL3-006, ERT-TX49H4-008 + * + * Workaround: mask EXL bit of the result or place a nop before mfc0. + */ +__asm__ ( + " .macro raw_local_irq_disable\n" + " .set push \n" + " .set noat \n" +#ifdef CONFIG_MIPS_MT_SMTC + " mfc0 $1, $2, 1 \n" + " ori $1, 0x400 \n" + " .set noreorder \n" + " mtc0 $1, $2, 1 \n" +#elif defined(CONFIG_CPU_MIPSR2) + " di \n" +#else + " mfc0 $1,$12 \n" + " ori $1,0x1f \n" + " xori $1,0x1f \n" + " .set noreorder \n" + " mtc0 $1,$12 \n" +#endif + " irq_disable_hazard \n" + " .set pop \n" + " .endm \n"); + +static inline void raw_local_irq_disable(void) +{ + __asm__ __volatile__( + "raw_local_irq_disable" + : /* no outputs */ + : /* no inputs */ + : "memory"); +} + +__asm__ ( + " .macro raw_local_save_flags flags \n" + " .set push \n" + " .set reorder \n" +#ifdef CONFIG_MIPS_MT_SMTC + " mfc0 \\flags, $2, 1 \n" +#else + " mfc0 \\flags, $12 \n" +#endif + " .set pop \n" + " .endm \n"); + +#define raw_local_save_flags(x) \ +__asm__ __volatile__( \ + "raw_local_save_flags %0" \ + : "=r" (x)) + +__asm__ ( + " .macro raw_local_irq_save result \n" + " .set push \n" + " .set reorder \n" + " .set noat \n" +#ifdef CONFIG_MIPS_MT_SMTC + " mfc0 \\result, $2, 1 \n" + " ori $1, \\result, 0x400 \n" + " .set noreorder \n" + " mtc0 $1, $2, 1 \n" + " andi \\result, \\result, 0x400 \n" +#elif defined(CONFIG_CPU_MIPSR2) + " di \\result \n" + " andi \\result, 1 \n" +#else + " mfc0 \\result, $12 \n" + " ori $1, \\result, 0x1f \n" + " xori $1, 0x1f \n" + " .set noreorder \n" + " mtc0 $1, $12 \n" +#endif + " irq_disable_hazard \n" + " .set pop \n" + " .endm \n"); + +#define raw_local_irq_save(x) \ +__asm__ __volatile__( \ + "raw_local_irq_save\t%0" \ + : "=r" (x) \ + : /* no inputs */ \ + : "memory") + +__asm__ ( + " .macro raw_local_irq_restore flags \n" + " .set push \n" + " .set noreorder \n" + " .set noat \n" +#ifdef CONFIG_MIPS_MT_SMTC + "mfc0 $1, $2, 1 \n" + "andi \\flags, 0x400 \n" + "ori $1, 0x400 \n" + "xori $1, 0x400 \n" + "or \\flags, $1 \n" + "mtc0 \\flags, $2, 1 \n" +#elif defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU) + /* + * Slow, but doesn't suffer from a relativly unlikely race + * condition we're having since days 1. + */ + " beqz \\flags, 1f \n" + " di \n" + " ei \n" + "1: \n" +#elif defined(CONFIG_CPU_MIPSR2) + /* + * Fast, dangerous. Life is fun, life is good. + */ + " mfc0 $1, $12 \n" + " ins $1, \\flags, 0, 1 \n" + " mtc0 $1, $12 \n" +#else + " mfc0 $1, $12 \n" + " andi \\flags, 1 \n" + " ori $1, 0x1f \n" + " xori $1, 0x1f \n" + " or \\flags, $1 \n" + " mtc0 \\flags, $12 \n" +#endif + " irq_disable_hazard \n" + " .set pop \n" + " .endm \n"); + +#define raw_local_irq_restore(flags) \ +do { \ + unsigned long __tmp1; \ + \ + __asm__ __volatile__( \ + "raw_local_irq_restore\t%0" \ + : "=r" (__tmp1) \ + : "0" (flags) \ + : "memory"); \ +} while(0) + +static inline int raw_irqs_disabled_flags(unsigned long flags) +{ +#ifdef CONFIG_MIPS_MT_SMTC + /* + * SMTC model uses TCStatus.IXMT to disable interrupts for a thread/CPU + */ + return flags & 0x400; +#else + return !(flags & 1); +#endif +} + +#endif + +/* + * Do the CPU's IRQ-state tracing from assembly code. + */ +#ifdef CONFIG_TRACE_IRQFLAGS +# define TRACE_IRQS_ON \ + jal trace_hardirqs_on +# define TRACE_IRQS_OFF \ + jal trace_hardirqs_off +#else +# define TRACE_IRQS_ON +# define TRACE_IRQS_OFF +#endif + +#endif /* _ASM_IRQFLAGS_H */ diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h index b4169f0fb13b3..677668867b9d7 100644 --- a/include/asm-mips/mipsregs.h +++ b/include/asm-mips/mipsregs.h @@ -1417,7 +1417,7 @@ change_c0_##name(unsigned int change, unsigned int new) \ #else /* SMTC versions that manage MT scheduling */ -#include +#include /* * This is a duplicate of dmt() in mipsmtregs.h to avoid problems with diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h index 130333d7c4ee8..13c98dde82dcd 100644 --- a/include/asm-mips/system.h +++ b/include/asm-mips/system.h @@ -13,13 +13,13 @@ #define _ASM_SYSTEM_H #include +#include #include #include #include #include #include -#include /* * read_barrier_depends - Flush all pending reads that subsequents reads -- cgit 1.2.3-korg