aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-mips
diff options
context:
space:
mode:
Diffstat (limited to 'include/asm-mips')
-rw-r--r--include/asm-mips/bootinfo.h12
-rw-r--r--include/asm-mips/cacheflush.h2
-rw-r--r--include/asm-mips/galileo-boards/ev96100.h55
-rw-r--r--include/asm-mips/galileo-boards/ev96100int.h12
-rw-r--r--include/asm-mips/irqflags.h25
-rw-r--r--include/asm-mips/it8172/it8172.h348
-rw-r--r--include/asm-mips/it8172/it8172_cir.h140
-rw-r--r--include/asm-mips/it8172/it8172_dbg.h38
-rw-r--r--include/asm-mips/it8172/it8172_int.h144
-rw-r--r--include/asm-mips/it8172/it8172_pci.h108
-rw-r--r--include/asm-mips/it8712.h28
-rw-r--r--include/asm-mips/mach-ev64120/mach-gt64120.h1
-rw-r--r--include/asm-mips/mach-ip27/topology.h1
-rw-r--r--include/asm-mips/ptrace.h3
-rw-r--r--include/asm-mips/serial.h51
-rw-r--r--include/asm-mips/stacktrace.h44
-rw-r--r--include/asm-mips/tx4938/tx4938_mips.h2
-rw-r--r--include/asm-mips/unistd.h39
18 files changed, 81 insertions, 972 deletions
diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h
index 78c35ec463624..1e5ccdad3b021 100644
--- a/include/asm-mips/bootinfo.h
+++ b/include/asm-mips/bootinfo.h
@@ -125,12 +125,6 @@
#define MACH_MOMENCO_OCELOT_3 4
/*
- * Valid machtype for group ITE
- */
-#define MACH_GROUP_ITE 13 /* ITE Semi Eval Boards */
-#define MACH_QED_4N_S01B 0 /* ITE8172 based eval board */
-
-/*
* Valid machtype for group PHILIPS
*/
#define MACH_GROUP_PHILIPS 14
@@ -139,12 +133,6 @@
#define MACH_PHILIPS_JBS 2 /* JBS */
/*
- * Valid machtype for group Globespan
- */
-#define MACH_GROUP_GLOBESPAN 15 /* Globespan */
-#define MACH_IVR 0 /* IVR eval board */
-
-/*
* Valid machtype for group SIBYTE
*/
#define MACH_GROUP_SIBYTE 16 /* Sibyte / Broadcom */
diff --git a/include/asm-mips/cacheflush.h b/include/asm-mips/cacheflush.h
index 36416fdfcf689..9ab59e2bb2336 100644
--- a/include/asm-mips/cacheflush.h
+++ b/include/asm-mips/cacheflush.h
@@ -46,8 +46,6 @@ static inline void flush_dcache_page(struct page *page)
#define flush_dcache_mmap_lock(mapping) do { } while (0)
#define flush_dcache_mmap_unlock(mapping) do { } while (0)
-extern void (*__flush_icache_page)(struct vm_area_struct *vma,
- struct page *page);
static inline void flush_icache_page(struct vm_area_struct *vma,
struct page *page)
{
diff --git a/include/asm-mips/galileo-boards/ev96100.h b/include/asm-mips/galileo-boards/ev96100.h
deleted file mode 100644
index 070dfd84a8e86..0000000000000
--- a/include/asm-mips/galileo-boards/ev96100.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- *
- */
-#ifndef _MIPS_EV96100_H
-#define _MIPS_EV96100_H
-
-#include <asm/addrspace.h>
-
-/*
- * GT64120 config space base address
- */
-#define GT64120_BASE (KSEG1ADDR(0x14000000))
-#define MIPS_GT_BASE GT64120_BASE
-
-/*
- * PCI Bus allocation
- */
-#define GT_PCI_MEM_BASE 0x12000000UL
-#define GT_PCI_MEM_SIZE 0x02000000UL
-#define GT_PCI_IO_BASE 0x10000000UL
-#define GT_PCI_IO_SIZE 0x02000000UL
-#define GT_ISA_IO_BASE PCI_IO_BASE
-
-/*
- * Duart I/O ports.
- */
-#define EV96100_COM1_BASE_ADDR (0xBD000000 + 0x20)
-#define EV96100_COM2_BASE_ADDR (0xBD000000 + 0x00)
-
-
-/*
- * EV96100 interrupt controller register base.
- */
-#define EV96100_ICTRL_REGS_BASE (KSEG1ADDR(0x1f000000))
-
-/*
- * EV96100 UART register base.
- */
-#define EV96100_UART0_REGS_BASE EV96100_COM1_BASE_ADDR
-#define EV96100_UART1_REGS_BASE EV96100_COM2_BASE_ADDR
-#define EV96100_BASE_BAUD ( 3686400 / 16 )
-
-
-/*
- * Because of an error/peculiarity in the Galileo chip, we need to swap the
- * bytes when running bigendian.
- */
-#define __GT_READ(ofs) \
- (*(volatile u32 *)(GT64120_BASE+(ofs)))
-#define __GT_WRITE(ofs, data) \
- do { *(volatile u32 *)(GT64120_BASE+(ofs)) = (data); } while (0)
-#define GT_READ(ofs) le32_to_cpu(__GT_READ(ofs))
-#define GT_WRITE(ofs, data) __GT_WRITE(ofs, cpu_to_le32(data))
-
-#endif /* !(_MIPS_EV96100_H) */
diff --git a/include/asm-mips/galileo-boards/ev96100int.h b/include/asm-mips/galileo-boards/ev96100int.h
deleted file mode 100644
index c58b16d06d6e8..0000000000000
--- a/include/asm-mips/galileo-boards/ev96100int.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- *
- */
-#ifndef _MIPS_EV96100INT_H
-#define _MIPS_EV96100INT_H
-
-#define EV96100INT_UART_0 6 /* IP 6 */
-#define EV96100INT_TIMER 7 /* IP 7 */
-
-extern void ev96100int_init(void);
-
-#endif /* !(_MIPS_EV96100_H) */
diff --git a/include/asm-mips/irqflags.h b/include/asm-mips/irqflags.h
index 43ca09a3a3d0c..46bf5de5ac720 100644
--- a/include/asm-mips/irqflags.h
+++ b/include/asm-mips/irqflags.h
@@ -213,12 +213,37 @@ static inline int raw_irqs_disabled_flags(unsigned long flags)
* Do the CPU's IRQ-state tracing from assembly code.
*/
#ifdef CONFIG_TRACE_IRQFLAGS
+/* Reload some registers clobbered by trace_hardirqs_on */
+#ifdef CONFIG_64BIT
+# define TRACE_IRQS_RELOAD_REGS \
+ LONG_L $11, PT_R11(sp); \
+ LONG_L $10, PT_R10(sp); \
+ LONG_L $9, PT_R9(sp); \
+ LONG_L $8, PT_R8(sp); \
+ LONG_L $7, PT_R7(sp); \
+ LONG_L $6, PT_R6(sp); \
+ LONG_L $5, PT_R5(sp); \
+ LONG_L $4, PT_R4(sp); \
+ LONG_L $2, PT_R2(sp)
+#else
+# define TRACE_IRQS_RELOAD_REGS \
+ LONG_L $7, PT_R7(sp); \
+ LONG_L $6, PT_R6(sp); \
+ LONG_L $5, PT_R5(sp); \
+ LONG_L $4, PT_R4(sp); \
+ LONG_L $2, PT_R2(sp)
+#endif
# define TRACE_IRQS_ON \
+ CLI; /* make sure trace_hardirqs_on() is called in kernel level */ \
jal trace_hardirqs_on
+# define TRACE_IRQS_ON_RELOAD \
+ TRACE_IRQS_ON; \
+ TRACE_IRQS_RELOAD_REGS
# define TRACE_IRQS_OFF \
jal trace_hardirqs_off
#else
# define TRACE_IRQS_ON
+# define TRACE_IRQS_ON_RELOAD
# define TRACE_IRQS_OFF
#endif
diff --git a/include/asm-mips/it8172/it8172.h b/include/asm-mips/it8172/it8172.h
deleted file mode 100644
index 8f23af0a1ee87..0000000000000
--- a/include/asm-mips/it8172/it8172.h
+++ /dev/null
@@ -1,348 +0,0 @@
-/*
- *
- * BRIEF MODULE DESCRIPTION
- * IT8172 system controller defines.
- *
- * Copyright 2000 MontaVista Software Inc.
- * Author: MontaVista Software, Inc.
- * ppopov@mvista.com or source@mvista.com
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __IT8172__H__
-#define __IT8172__H__
-
-#include <asm/addrspace.h>
-
-#define IT8172_BASE 0x18000000
-#define IT8172_PCI_IO_BASE 0x14000000
-#define IT8172_PCI_MEM_BASE 0x10000000
-
-// System registers offsets from IT8172_BASE
-#define IT_CMFPCR 0x0
-#define IT_DSRR 0x2
-#define IT_PCDCR 0x4
-#define IT_SPLLCR 0x6
-#define IT_CIDR 0x10
-#define IT_CRNR 0x12
-#define IT_CPUTR 0x14
-#define IT_CTCR 0x16
-#define IT_SDPR 0xF0
-
-// Power management register offset from IT8172_PCI_IO_BASE
-// Power Management Device Standby Register
-#define IT_PM_DSR 0x15800
-
-#define IT_PM_DSR_TMR0SB 0x0001
-#define IT_PM_DSR_TMR1SB 0x0002
-#define IT_PM_DSR_CIR0SB 0x0004
-#define IT_PM_DSR_CIR1SB 0x0008
-#define IT_PM_DSR_SCR0SB 0x0010
-#define IT_PM_DSR_SCR1SB 0x0020
-#define IT_PM_DSR_PPSB 0x0040
-#define IT_PM_DSR_I2CSB 0x0080
-#define IT_PM_DSR_UARTSB 0x0100
-#define IT_PM_DSR_IDESB 0x0200
-#define IT_PM_DSR_ACSB 0x0400
-#define IT_PM_DSR_M68KSB 0x0800
-
-// Power Management PCI Device Software Reset Register
-#define IT_PM_PCISR 0x15802
-
-#define IT_PM_PCISR_IDESR 0x0001
-#define IT_PM_PCISR_CDMASR 0x0002
-#define IT_PM_PCISR_USBSR 0x0004
-#define IT_PM_PCISR_DMASR 0x0008
-#define IT_PM_PCISR_ACSR 0x0010
-#define IT_PM_PCISR_MEMSR 0x0020
-#define IT_PM_PCISR_68KSR 0x0040
-
-
-// PCI Configuration address and data register offsets
-// from IT8172_BASE
-#define IT_CONFADDR 0x4000
-#define IT_BUSNUM_SHF 16
-#define IT_DEVNUM_SHF 11
-#define IT_FUNCNUM_SHF 8
-#define IT_REGNUM_SHF 2
-
-#define IT_CONFDATA 0x4004
-
-// PCI configuration header common register offsets
-#define IT_VID 0x00
-#define IT_DID 0x02
-#define IT_PCICMD 0x04
-#define IT_PCISTS 0x06
-#define IT_RID 0x08
-#define IT_CLASSC 0x09
-#define IT_HEADT 0x0E
-#define IT_SERIRQC 0x49
-
-// PCI to Internal/LPC Bus Bridge configuration header register offset
-#define IT_P2I_BCR 0x4C
-#define IT_P2I_D0IOSC 0x50
-#define IT_P2I_D1IOSC 0x54
-#define IT_P2I_D2IOSC 0x58
-#define IT_P2I_D3IOSC 0x5C
-#define IT_P2I_D4IOSC 0x60
-#define IT_P2I_D5IOSC 0x64
-#define IT_P2I_D6IOSC 0x68
-#define IT_P2I_D7IOSC 0x6C
-#define IT_P2I_D8IOSC 0x70
-#define IT_P2I_D9IOSC 0x74
-#define IT_P2I_D10IOSC 0x78
-#define IT_P2I_D11IOSC 0x7C
-
-// Memory controller register offsets from IT8172_BASE
-#define IT_MC_SDRMR 0x1000
-#define IT_MC_SDRTR 0x1004
-#define IT_MC_MCR 0x1008
-#define IT_MC_SDTYPE 0x100C
-#define IT_MC_WPBA 0x1010
-#define IT_MC_WPTA 0x1014
-#define IT_MC_HATR 0x1018
-#define IT_MC_PCICR 0x101C
-
-// Flash/ROM control register offsets from IT8172_BASE
-#define IT_FC_BRCR 0x2000
-#define IT_FC_FCR 0x2004
-#define IT_FC_DCR 0x2008
-
-// M68K interface bridge configuration header register offset
-#define IT_M68K_MBCSR 0x54
-#define IT_M68K_TMR 0x58
-#define IT_M68K_BCR 0x5C
-#define IT_M68K_BSR 0x5D
-#define IT_M68K_DTR 0x5F
-
-// Register offset from IT8172_PCI_IO_BASE
-// These registers are accessible through 8172 PCI IO window.
-
-// INTC
-#define IT_INTC_BASE 0x10000
-#define IT_INTC_LBDNIRR 0x10000
-#define IT_INTC_LBDNIMR 0x10002
-#define IT_INTC_LBDNITR 0x10004
-#define IT_INTC_LBDNIAR 0x10006
-#define IT_INTC_LPCNIRR 0x10010
-#define IT_INTC_LPCNIMR 0x10012
-#define IT_INTC_LPCNITR 0x10014
-#define IT_INTC_LPCNIAR 0x10016
-#define IT_INTC_PDNIRR 0x10020
-#define IT_INTC_PDNIMR 0x10022
-#define IT_INTC_PDNITR 0x10024
-#define IT_INTC_PDNIAR 0x10026
-#define IT_INTC_UMNIRR 0x10030
-#define IT_INTC_UMNITR 0x10034
-#define IT_INTC_UMNIAR 0x10036
-#define IT_INTC_TYPER 0x107FE
-
-// IT8172 PCI device number
-#define IT_C2P_DEVICE 0
-#define IT_AUDIO_DEVICE 1
-#define IT_DMAC_DEVICE 1
-#define IT_CDMAC_DEVICE 1
-#define IT_USB_DEVICE 1
-#define IT_P2I_DEVICE 1
-#define IT_IDE_DEVICE 1
-#define IT_M68K_DEVICE 1
-
-// IT8172 PCI function number
-#define IT_C2P_FUNCION 0
-#define IT_AUDIO_FUNCTION 0
-#define IT_DMAC_FUNCTION 1
-#define IT_CDMAC_FUNCTION 2
-#define IT_USB_FUNCTION 3
-#define IT_P2I_FUNCTION 4
-#define IT_IDE_FUNCTION 5
-#define IT_M68K_FUNCTION 6
-
-// IT8172 GPIO
-#define IT_GPADR 0x13800
-#define IT_GPBDR 0x13808
-#define IT_GPCDR 0x13810
-#define IT_GPACR 0x13802
-#define IT_GPBCR 0x1380A
-#define IT_GPCCR 0x13812
-#define IT_GPAICR 0x13804
-#define IT_GPBICR 0x1380C
-#define IT_GPCICR 0x13814
-#define IT_GPAISR 0x13806
-#define IT_GPBISR 0x1380E
-#define IT_GPCISR 0x13816
-#define IT_GCR 0x13818
-
-// IT8172 RTC
-#define IT_RTC_BASE 0x14800
-#define IT_RTC_CENTURY 0x14808
-
-#define IT_RTC_RIR0 0x00
-#define IT_RTC_RTR0 0x01
-#define IT_RTC_RIR1 0x02
-#define IT_RTC_RTR1 0x03
-#define IT_RTC_RIR2 0x04
-#define IT_RTC_RTR2 0x05
-#define IT_RTC_RCTR 0x08
-#define IT_RTC_RA 0x0A
-#define IT_RTC_RB 0x0B
-#define IT_RTC_RC 0x0C
-#define IT_RTC_RD 0x0D
-
-#define RTC_SEC_INDEX 0x00
-#define RTC_MIN_INDEX 0x02
-#define RTC_HOUR_INDEX 0x04
-#define RTC_DAY_INDEX 0x06
-#define RTC_DATE_INDEX 0x07
-#define RTC_MONTH_INDEX 0x08
-#define RTC_YEAR_INDEX 0x09
-
-// IT8172 internal device registers
-#define IT_TIMER_BASE 0x10800
-#define IT_CIR0_BASE 0x11000
-#define IT_UART_BASE 0x11800
-#define IT_SCR0_BASE 0x12000
-#define IT_SCR1_BASE 0x12800
-#define IT_PP_BASE 0x13000
-#define IT_I2C_BASE 0x14000
-#define IT_CIR1_BASE 0x15000
-
-// IT8172 Smart Card Reader offsets from IT_SCR*_BASE
-#define IT_SCR_SFR 0x08
-#define IT_SCR_SCDR 0x09
-
-// IT8172 IT_SCR_SFR bit definition & mask
-#define IT_SCR_SFR_GATE_UART 0x40
-#define IT_SCR_SFR_GATE_UART_BIT 6
-#define IT_SCR_SFR_GATE_UART_OFF 0
-#define IT_SCR_SFR_GATE_UART_ON 1
-#define IT_SCR_SFR_FET_CHARGE 0x30
-#define IT_SCR_SFR_FET_CHARGE_BIT 4
-#define IT_SCR_SFR_FET_CHARGE_3_3_US 3
-#define IT_SCR_SFR_FET_CHARGE_13_US 2
-#define IT_SCR_SFR_FET_CHARGE_53_US 1
-#define IT_SCR_SFR_FET_CHARGE_213_US 0
-#define IT_SCR_SFR_CARD_FREQ 0x0C
-#define IT_SCR_SFR_CARD_FREQ_BIT 2
-#define IT_SCR_SFR_CARD_FREQ_STOP 3
-#define IT_SCR_SFR_CARD_FREQ_3_5_MHZ 0
-#define IT_SCR_SFR_CARD_FREQ_7_1_MHZ 2
-#define IT_SCR_SFR_CARD_FREQ_96_DIV_MHZ 1
-#define IT_SCR_SFR_FET_ACTIVE 0x02
-#define IT_SCR_SFR_FET_ACTIVE_BIT 1
-#define IT_SCR_SFR_FET_ACTIVE_INVERT 0
-#define IT_SCR_SFR_FET_ACTIVE_NONINVERT 1
-#define IT_SCR_SFR_ENABLE 0x01
-#define IT_SCR_SFR_ENABLE_BIT 0
-#define IT_SCR_SFR_ENABLE_OFF 0
-#define IT_SCR_SFR_ENABLE_ON 1
-
-// IT8172 IT_SCR_SCDR bit definition & mask
-#define IT_SCR_SCDR_RESET_MODE 0x80
-#define IT_SCR_SCDR_RESET_MODE_BIT 7
-#define IT_SCR_SCDR_RESET_MODE_ASYNC 0
-#define IT_SCR_SCDR_RESET_MODE_SYNC 1
-#define IT_SCR_SCDR_DIVISOR 0x7F
-#define IT_SCR_SCDR_DIVISOR_BIT 0
-#define IT_SCR_SCDR_DIVISOR_STOP_VAL_1 0x00
-#define IT_SCR_SCDR_DIVISOR_STOP_VAL_2 0x01
-#define IT_SCR_SCDR_DIVISOR_STOP_VAL_3 0x7F
-
-// IT8172 DMA
-#define IT_DMAC_BASE 0x16000
-#define IT_DMAC_BCAR0 0x00
-#define IT_DMAC_BCAR1 0x04
-#define IT_DMAC_BCAR2 0x08
-#define IT_DMAC_BCAR3 0x0C
-#define IT_DMAC_BCCR0 0x02
-#define IT_DMAC_BCCR1 0x06
-#define IT_DMAC_BCCR2 0x0a
-#define IT_DMAC_BCCR3 0x0e
-#define IT_DMAC_CR 0x10
-#define IT_DMAC_SR 0x12
-#define IT_DMAC_ESR 0x13
-#define IT_DMAC_RQR 0x14
-#define IT_DMAC_MR 0x16
-#define IT_DMAC_EMR 0x17
-#define IT_DMAC_MKR 0x18
-#define IT_DMAC_PAR0 0x20
-#define IT_DMAC_PAR1 0x22
-#define IT_DMAC_PAR2 0x24
-#define IT_DMAC_PAR3 0x26
-
-// IT8172 IDE
-#define IT_IDE_BASE 0x17800
-#define IT_IDE_STATUS 0x1F7
-
-// IT8172 Audio Controller
-#define IT_AC_BASE 0x17000
-#define IT_AC_PCMOV 0x00
-#define IT_AC_FMOV 0x02
-#define IT_AC_I2SV 0x04
-#define IT_AC_DRSS 0x06
-#define IT_AC_PCC 0x08
-#define IT_AC_PCDL 0x0A
-#define IT_AC_PCB1STA 0x0C
-#define IT_AC_PCB2STA 0x10
-#define IT_AC_CAPCC 0x14
-#define IT_AC_CAPCDL 0x16
-#define IT_AC_CAPB1STA 0x18
-#define IT_AC_CAPB2STA 0x1C
-#define IT_AC_CODECC 0x22
-#define IT_AC_I2SMC 0x24
-#define IT_AC_VS 0x26
-#define IT_AC_SRCS 0x28
-#define IT_AC_CIRCP 0x2A
-#define IT_AC_CIRDP 0x2C
-#define IT_AC_TM 0x4A
-#define IT_AC_PFDP 0x4C
-#define IT_AC_GC 0x54
-#define IT_AC_IMC 0x56
-#define IT_AC_ISC 0x5B
-#define IT_AC_OPL3SR 0x68
-#define IT_AC_OPL3DWDR 0x69
-#define IT_AC_OPL3AB1W 0x6A
-#define IT_AC_OPL3DW 0x6B
-#define IT_AC_BPDC 0x70
-
-
-// IT8172 Timer
-#define IT_TIMER_BASE 0x10800
-#define TIMER_TCVR0 0x00
-#define TIMER_TRVR0 0x02
-#define TIMER_TCR0 0x04
-#define TIMER_TIRR 0x06
-#define TIMER_TCVR1 0x08
-#define TIMER_TRVR1 0x0A
-#define TIMER_TCR1 0x0C
-#define TIMER_TIDR 0x0E
-
-
-#define IT_WRITE(ofs, data) *(volatile u32 *)KSEG1ADDR((IT8172_BASE+ofs)) = data
-#define IT_READ(ofs, data) data = *(volatile u32 *)KSEG1ADDR((IT8172_BASE+ofs))
-
-#define IT_IO_WRITE(ofs, data) *(volatile u32 *)KSEG1ADDR((IT8172_PCI_IO_BASE+ofs)) = data
-#define IT_IO_READ(ofs, data) data = *(volatile u32 *)KSEG1ADDR((IT8172_PCI_IO_BASE+ofs))
-
-#define IT_IO_WRITE16(ofs, data) *(volatile u16 *)KSEG1ADDR((IT8172_PCI_IO_BASE+ofs)) = data
-#define IT_IO_READ16(ofs, data) data = *(volatile u16 *)KSEG1ADDR((IT8172_PCI_IO_BASE+ofs))
-
-#endif
diff --git a/include/asm-mips/it8172/it8172_cir.h b/include/asm-mips/it8172/it8172_cir.h
deleted file mode 100644
index 6a1dbd29f6d19..0000000000000
--- a/include/asm-mips/it8172/it8172_cir.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- *
- * BRIEF MODULE DESCRIPTION
- * IT8172 Consumer IR port defines.
- *
- * Copyright 2001 MontaVista Software Inc.
- * Author: MontaVista Software, Inc.
- * ppopov@mvista.com or source@mvista.com
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#define NUM_CIR_PORTS 2
-
-/* Master Control Register */
-#define CIR_RESET 0x1
-#define CIR_FIFO_CLEAR 0x2
-#define CIR_SET_FIFO_TL(x) (((x)&0x3)<<2)
-#define CIR_ILE 0x10
-#define CIR_ILSEL 0x20
-
-/* Interrupt Enable Register */
-#define CIR_TLDLIE 0x1
-#define CIR_RDAIE 0x2
-#define CIR_RFOIE 0x4
-#define CIR_IEC 0x80
-
-/* Interrupt Identification Register */
-#define CIR_TLDLI 0x1
-#define CIR_RDAI 0x2
-#define CIR_RFOI 0x4
-#define CIR_NIP 0x80
-
-/* Carrier Frequency Register */
-#define CIR_SET_CF(x) ((x)&0x1f)
- #define CFQ_38_480 0xB /* 38 KHz low, 480 KHz high */
-#define CIR_HCFS 0x20
- #define CIR_SET_HS(x) (((x)&0x1)<<5)
-
-
-/* Receiver Control Register */
-#define CIR_SET_RXDCR(x) ((x)&0x7)
-#define CIR_RXACT 0x8
-#define CIR_RXEND 0x10
-#define CIR_RDWOS 0x20
- #define CIR_SET_RDWOS(x) (((x)&0x1)<<5)
-#define CIR_RXEN 0x80
-
-/* Transmitter Control Register */
-#define CIR_SET_TXMPW(x) ((x)&0x7)
-#define CIR_SET_TXMPM(x) (((x)&0x3)<<3)
-#define CIR_TXENDF 0x20
-#define CIR_TXRLE 0x40
-
-/* Receiver FIFO Status Register */
-#define CIR_RXFBC_MASK 0x3f
-#define CIR_RXFTO 0x80
-
-/* Wakeup Code Length Register */
-#define CIR_SET_WCL ((x)&0x3f)
-#define CIR_WCL_MASK(x) ((x)&0x3f)
-
-/* Wakeup Power Control/Status Register */
-#define CIR_BTMON 0x2
-#define CIR_CIRON 0x4
-#define CIR_RCRST 0x10
-#define CIR_WCRST 0x20
-
-struct cir_port {
- int port;
- unsigned short baud_rate;
- unsigned char fifo_tl;
- unsigned char cfq;
- unsigned char hcfs;
- unsigned char rdwos;
- unsigned char rxdcr;
-};
-
-struct it8172_cir_regs {
- unsigned char dr; /* data */
- char pad;
- unsigned char mstcr; /* master control */
- char pad1;
- unsigned char ier; /* interrupt enable */
- char pad2;
- unsigned char iir; /* interrupt identification */
- char pad3;
- unsigned char cfr; /* carrier frequency */
- char pad4;
- unsigned char rcr; /* receiver control */
- char pad5;
- unsigned char tcr; /* transmitter control */
- char pad6;
- char pad7;
- char pad8;
- unsigned char bdlr; /* baud rate divisor low byte */
- char pad9;
- unsigned char bdhr; /* baud rate divisor high byte */
- char pad10;
- unsigned char tfsr; /* tx fifo byte count */
- char pad11;
- unsigned char rfsr; /* rx fifo status */
- char pad12;
- unsigned char wcl; /* wakeup code length */
- char pad13;
- unsigned char wcr; /* wakeup code read/write */
- char pad14;
- unsigned char wps; /* wakeup power control/status */
-};
-
-int cir_port_init(struct cir_port *cir);
-extern void clear_fifo(struct cir_port *cir);
-extern void enable_receiver(struct cir_port *cir);
-extern void disable_receiver(struct cir_port *cir);
-extern void enable_rx_demodulation(struct cir_port *cir);
-extern void disable_rx_demodulation(struct cir_port *cir);
-extern void set_rx_active(struct cir_port *cir);
-extern void int_enable(struct cir_port *cir);
-extern void rx_int_enable(struct cir_port *cir);
-extern char get_int_status(struct cir_port *cir);
-extern int cir_get_rx_count(struct cir_port *cir);
-extern char cir_read_data(struct cir_port *cir);
diff --git a/include/asm-mips/it8172/it8172_dbg.h b/include/asm-mips/it8172/it8172_dbg.h
deleted file mode 100644
index f404ec7c03acf..0000000000000
--- a/include/asm-mips/it8172/it8172_dbg.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- *
- * BRIEF MODULE DESCRIPTION
- * Function prototypes for low level uart routines to
- * directly access a 16550 uart.
- *
- * Copyright 2000 MontaVista Software Inc.
- * Author: MontaVista Software, Inc.
- * ppopov@mvista.com or source@mvista.com
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/types.h>
-
-extern void putch(const unsigned char c);
-extern void puts(unsigned char *cp);
-extern void fputs(unsigned char *cp);
-extern void put64(uint64_t ul);
-extern void put32(unsigned u);
diff --git a/include/asm-mips/it8172/it8172_int.h b/include/asm-mips/it8172/it8172_int.h
deleted file mode 100644
index 837e83ac25f50..0000000000000
--- a/include/asm-mips/it8172/it8172_int.h
+++ /dev/null
@@ -1,144 +0,0 @@
-/*
- *
- * BRIEF MODULE DESCRIPTION
- * ITE 8172 Interrupt Numbering
- *
- * Copyright 2000 MontaVista Software Inc.
- * Author: MontaVista Software, Inc.
- * ppopov@mvista.com or source@mvista.com
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef _MIPS_ITEINT_H
-#define _MIPS_ITEINT_H
-
-/*
- * Here's the "strategy":
- * We number the LPC serial irqs from 0 to 15,
- * the local bus irqs from 16 to 31,
- * the pci dev register interrupts from 32 to 47,
- * and the non-maskable ints from 48 to 53.
- */
-
-#define IT8172_LPC_IRQ_BASE 0 /* first LPC int number */
-#define IT8172_SERIRQ_0 (IT8172_LPC_IRQ_BASE + 0)
-#define IT8172_SERIRQ_1 (IT8172_LPC_IRQ_BASE + 1)
-#define IT8172_SERIRQ_2 (IT8172_LPC_IRQ_BASE + 2)
-#define IT8172_SERIRQ_3 (IT8172_LPC_IRQ_BASE + 3)
-#define IT8172_SERIRQ_4 (IT8172_LPC_IRQ_BASE + 4)
-#define IT8172_SERIRQ_5 (IT8172_LPC_IRQ_BASE + 5)
-#define IT8172_SERIRQ_6 (IT8172_LPC_IRQ_BASE + 6)
-#define IT8172_SERIRQ_7 (IT8172_LPC_IRQ_BASE + 7)
-#define IT8172_SERIRQ_8 (IT8172_LPC_IRQ_BASE + 8)
-#define IT8172_SERIRQ_9 (IT8172_LPC_IRQ_BASE + 9)
-#define IT8172_SERIRQ_10 (IT8172_LPC_IRQ_BASE + 10)
-#define IT8172_SERIRQ_11 (IT8172_LPC_IRQ_BASE + 11)
-#define IT8172_SERIRQ_12 (IT8172_LPC_IRQ_BASE + 12)
-#define IT8172_SERIRQ_13 (IT8172_LPC_IRQ_BASE + 13)
-#define IT8172_SERIRQ_14 (IT8172_LPC_IRQ_BASE + 14)
-#define IT8172_SERIRQ_15 (IT8172_LPC_IRQ_BASE + 15)
-
-#define IT8172_LB_IRQ_BASE 16 /* first local bus int number */
-#define IT8172_PPR_IRQ (IT8172_LB_IRQ_BASE + 0) /* parallel port */
-#define IT8172_TIMER0_IRQ (IT8172_LB_IRQ_BASE + 1)
-#define IT8172_TIMER1_IRQ (IT8172_LB_IRQ_BASE + 2)
-#define IT8172_I2C_IRQ (IT8172_LB_IRQ_BASE + 3)
-#define IT8172_GPIO_IRQ (IT8172_LB_IRQ_BASE + 4)
-#define IT8172_CIR0_IRQ (IT8172_LB_IRQ_BASE + 5)
-#define IT8172_CIR1_IRQ (IT8172_LB_IRQ_BASE + 6)
-#define IT8172_UART_IRQ (IT8172_LB_IRQ_BASE + 7)
-#define IT8172_SCR0_IRQ (IT8172_LB_IRQ_BASE + 8)
-#define IT8172_SCR1_IRQ (IT8172_LB_IRQ_BASE + 9)
-#define IT8172_RTC_IRQ (IT8172_LB_IRQ_BASE + 10)
-#define IT8172_IOCHK_IRQ (IT8172_LB_IRQ_BASE + 11)
-/* 12 - 15 reserved */
-
-/*
- * Note here that the pci dev registers includes bits for more than
- * just the pci devices.
- */
-#define IT8172_PCI_DEV_IRQ_BASE 32 /* first pci dev irq */
-#define IT8172_AC97_IRQ (IT8172_PCI_DEV_IRQ_BASE + 0)
-#define IT8172_MC68K_IRQ (IT8172_PCI_DEV_IRQ_BASE + 1)
-#define IT8172_IDE_IRQ (IT8172_PCI_DEV_IRQ_BASE + 2)
-#define IT8172_USB_IRQ (IT8172_PCI_DEV_IRQ_BASE + 3)
-#define IT8172_BRIDGE_MASTER_IRQ (IT8172_PCI_DEV_IRQ_BASE + 4)
-#define IT8172_BRIDGE_TARGET_IRQ (IT8172_PCI_DEV_IRQ_BASE + 5)
-#define IT8172_PCI_INTA_IRQ (IT8172_PCI_DEV_IRQ_BASE + 6)
-#define IT8172_PCI_INTB_IRQ (IT8172_PCI_DEV_IRQ_BASE + 7)
-#define IT8172_PCI_INTC_IRQ (IT8172_PCI_DEV_IRQ_BASE + 8)
-#define IT8172_PCI_INTD_IRQ (IT8172_PCI_DEV_IRQ_BASE + 9)
-#define IT8172_S_INTA_IRQ (IT8172_PCI_DEV_IRQ_BASE + 10)
-#define IT8172_S_INTB_IRQ (IT8172_PCI_DEV_IRQ_BASE + 11)
-#define IT8172_S_INTC_IRQ (IT8172_PCI_DEV_IRQ_BASE + 12)
-#define IT8172_S_INTD_IRQ (IT8172_PCI_DEV_IRQ_BASE + 13)
-#define IT8172_CDMA_IRQ (IT8172_PCI_DEV_IRQ_BASE + 14)
-#define IT8172_DMA_IRQ (IT8172_PCI_DEV_IRQ_BASE + 15)
-
-#define IT8172_NMI_IRQ_BASE 48
-#define IT8172_SER_NMI_IRQ (IT8172_NMI_IRQ_BASE + 0)
-#define IT8172_PCI_NMI_IRQ (IT8172_NMI_IRQ_BASE + 1)
-#define IT8172_RTC_NMI_IRQ (IT8172_NMI_IRQ_BASE + 2)
-#define IT8172_CPUIF_NMI_IRQ (IT8172_NMI_IRQ_BASE + 3)
-#define IT8172_PMER_NMI_IRQ (IT8172_NMI_IRQ_BASE + 4)
-#define IT8172_POWER_NMI_IRQ (IT8172_NMI_IRQ_BASE + 5)
-
-#define IT8172_LAST_IRQ (IT8172_POWER_NMI_IRQ)
-/* Finally, let's move over here the mips cpu timer interrupt.
- */
-#define MIPS_CPU_TIMER_IRQ (NR_IRQS-1)
-
-/*
- * IT8172 Interrupt Controller Registers
- */
-struct it8172_intc_regs {
- volatile unsigned short lb_req; /* offset 0 */
- volatile unsigned short lb_mask;
- volatile unsigned short lb_trigger;
- volatile unsigned short lb_level;
- unsigned char pad0[8];
-
- volatile unsigned short lpc_req; /* offset 0x10 */
- volatile unsigned short lpc_mask;
- volatile unsigned short lpc_trigger;
- volatile unsigned short lpc_level;
- unsigned char pad1[8];
-
- volatile unsigned short pci_req; /* offset 0x20 */
- volatile unsigned short pci_mask;
- volatile unsigned short pci_trigger;
- volatile unsigned short pci_level;
- unsigned char pad2[8];
-
- volatile unsigned short nmi_req; /* offset 0x30 */
- volatile unsigned short nmi_mask;
- volatile unsigned short nmi_trigger;
- volatile unsigned short nmi_level;
- unsigned char pad3[6];
-
- volatile unsigned short nmi_redir; /* offset 0x3E */
- unsigned char pad4[0xBE];
-
- volatile unsigned short intstatus; /* offset 0xFE */
-};
-
-#endif /* _MIPS_ITEINT_H */
diff --git a/include/asm-mips/it8172/it8172_pci.h b/include/asm-mips/it8172/it8172_pci.h
deleted file mode 100644
index 42c61f56eeba5..0000000000000
--- a/include/asm-mips/it8172/it8172_pci.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- *
- * BRIEF MODULE DESCRIPTION
- * IT8172 system controller specific pci defines.
- *
- * Copyright 2000 MontaVista Software Inc.
- * Author: MontaVista Software, Inc.
- * ppopov@mvista.com or source@mvista.com
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef _8172PCI_H_
-#define _8172PCI_H_
-
-// PCI configuration space Type0
-#define PCI_IDREG 0x00
-#define PCI_CMDSTSREG 0x04
-#define PCI_CLASSREG 0x08
-#define PCI_BHLCREG 0x0C
-#define PCI_BASE1REG 0x10
-#define PCI_BASE2REG 0x14
-#define PCI_BASE3REG 0x18
-#define PCI_BASE4REG 0x1C
-#define PCI_BASE5REG 0x20
-#define PCI_BASE6REG 0x24
-#define PCI_ROMBASEREG 0x30
-#define PCI_INTRREG 0x3C
-
-// PCI configuration space Type1
-#define PCI_BUSNOREG 0x18
-
-#define IT_PCI_VENDORID(x) ((x) & 0xFFFF)
-#define IT_PCI_DEVICEID(x) (((x)>>16) & 0xFFFF)
-
-// Command register
-#define PCI_CMD_IOEN 0x00000001
-#define PCI_CMD_MEMEN 0x00000002
-#define PCI_CMD_BUSMASTER 0x00000004
-#define PCI_CMD_SPCYCLE 0x00000008
-#define PCI_CMD_WRINV 0x00000010
-#define PCI_CMD_VGASNOOP 0x00000020
-#define PCI_CMD_PERR 0x00000040
-#define PCI_CMD_WAITCTRL 0x00000080
-#define PCI_CMD_SERR 0x00000100
-#define PCI_CMD_FAST_BACKTOBACK 0x00000200
-
-// Status register
-#define PCI_STS_66MHZ 0x00200000
-#define PCI_STS_SUPPORT_UDF 0x00400000
-#define PCI_STS_FAST_BACKTOBACK 0x00800000
-#define PCI_STS_DATA_PERR 0x01000000
-#define PCI_STS_DEVSEL0 0x02000000
-#define PCI_STS_DEVSEL1 0x04000000
-#define PCI_STS_SIG_TGTABORT 0x08000000
-#define PCI_STS_RCV_TGTABORT 0x10000000
-#define PCI_STS_RCV_MSTABORT 0x20000000
-#define PCI_STS_SYSERR 0x40000000
-#define PCI_STS_DETCT_PERR 0x80000000
-
-#define IT_PCI_CLASS(x) (((x)>>24) & 0xFF)
-#define IT_PCI_SUBCLASS(x) (((x)>>16) & 0xFF)
-#define IT_PCI_INTERFACE(x) (((x)>>8) & 0xFF)
-#define IT_PCI_REVISION(x) ((x) & 0xFF)
-
-// PCI class code
-#define PCI_CLASS_BRIDGE 0x06
-
-// bridge subclass
-#define PCI_SUBCLASS_BRIDGE_HOST 0x00
-#define PCI_SUBCLASS_BRIDGE_PCI 0x04
-
-// BHLCREG
-#define IT_PCI_BIST(x) (((x)>>24) & 0xFF)
-#define IT_PCI_HEADERTYPE(x) (((x)>>16) & 0xFF)
-#define IT_PCI_LATENCYTIMER(x) (((x)>>8) & 0xFF)
-#define IT_PCI_CACHELINESIZE(x) ((x) & 0xFF)
-
-#define PCI_MULTIFUNC 0x80
-
-// INTRREG
-#define IT_PCI_MAXLAT(x) (((x)>>24) & 0xFF)
-#define IT_PCI_MINGNT(x) (((x)>>16) & 0xFF)
-#define IT_PCI_INTRPIN(x) (((x)>>8) & 0xFF)
-#define IT_PCI_INTRLINE(x) ((x) & 0xFF)
-
-#define PCI_VENDOR_NEC 0x1033
-#define PCI_VENDOR_DEC 0x1101
-
-#endif // _8172PCI_H_
diff --git a/include/asm-mips/it8712.h b/include/asm-mips/it8712.h
deleted file mode 100644
index ca2dee02a011a..0000000000000
--- a/include/asm-mips/it8712.h
+++ /dev/null
@@ -1,28 +0,0 @@
-
-#ifndef __IT8712_H__
-#define __IT8712_H__
-
-#define LPC_BASE_ADDR 0x14000000
-
-// MB PnP configuration register
-#define LPC_KEY_ADDR 0x1400002E
-#define LPC_DATA_ADDR 0x1400002F
-
-// Device LDN
-#define LDN_SERIAL1 0x01
-#define LDN_SERIAL2 0x02
-#define LDN_PARALLEL 0x03
-#define LDN_KEYBOARD 0x05
-#define LDN_MOUSE 0x06
-
-#define IT8712_UART1_PORT 0x3F8
-#define IT8712_UART2_PORT 0x2F8
-
-#ifndef ASM_ONLY
-
-void LPCSetConfig(char LdnNumber, char Index, char data);
-char LPCGetConfig(char LdnNumber, char Index);
-
-#endif
-
-#endif
diff --git a/include/asm-mips/mach-ev64120/mach-gt64120.h b/include/asm-mips/mach-ev64120/mach-gt64120.h
index 13b1443a7a650..7e272ce57ea3a 100644
--- a/include/asm-mips/mach-ev64120/mach-gt64120.h
+++ b/include/asm-mips/mach-ev64120/mach-gt64120.h
@@ -42,6 +42,7 @@ extern unsigned long gt64120_base;
#define EV64120_UART0_REGS_BASE (KSEG1ADDR(EV64120_COM1_BASE_ADDR))
#define EV64120_UART1_REGS_BASE (KSEG1ADDR(EV64120_COM2_BASE_ADDR))
#define EV64120_BASE_BAUD ( 3686400 / 16 )
+#define EV64120_UART_IRQ 6
/*
* PCI interrupts will come in on either the INTA or INTD interrups lines,
diff --git a/include/asm-mips/mach-ip27/topology.h b/include/asm-mips/mach-ip27/topology.h
index 59d26b52ba321..a13b715fd9caf 100644
--- a/include/asm-mips/mach-ip27/topology.h
+++ b/include/asm-mips/mach-ip27/topology.h
@@ -22,6 +22,7 @@ extern unsigned char __node_distances[MAX_COMPACT_NODES][MAX_COMPACT_NODES];
#define SD_NODE_INIT (struct sched_domain) { \
.span = CPU_MASK_NONE, \
.parent = NULL, \
+ .child = NULL, \
.groups = NULL, \
.min_interval = 8, \
.max_interval = 32, \
diff --git a/include/asm-mips/ptrace.h b/include/asm-mips/ptrace.h
index 4fb0fc43ffd71..5f3a9075cd28e 100644
--- a/include/asm-mips/ptrace.h
+++ b/include/asm-mips/ptrace.h
@@ -44,9 +44,8 @@ struct pt_regs {
unsigned long cp0_epc;
#ifdef CONFIG_MIPS_MT_SMTC
unsigned long cp0_tcstatus;
- unsigned long smtc_pad;
#endif /* CONFIG_MIPS_MT_SMTC */
-};
+} __attribute__ ((aligned (8)));
/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
#define PTRACE_GETREGS 12
diff --git a/include/asm-mips/serial.h b/include/asm-mips/serial.h
index 035637c67e7c0..d7a65135d837e 100644
--- a/include/asm-mips/serial.h
+++ b/include/asm-mips/serial.h
@@ -55,51 +55,18 @@
* Galileo EV64120 evaluation board
*/
#ifdef CONFIG_MIPS_EV64120
-#include <asm/galileo-boards/ev96100.h>
-#include <asm/galileo-boards/ev96100int.h>
-#define EV96100_SERIAL_PORT_DEFNS \
- { .baud_base = EV96100_BASE_BAUD, .irq = EV96100INT_UART_0, \
+#include <mach-gt64120.h>
+#define EV64120_SERIAL_PORT_DEFNS \
+ { .baud_base = EV64120_BASE_BAUD, .irq = EV64120_UART_IRQ, \
.flags = STD_COM_FLAGS, \
- .iomem_base = EV96100_UART0_REGS_BASE, .iomem_reg_shift = 2, \
+ .iomem_base = EV64120_UART0_REGS_BASE, .iomem_reg_shift = 2, \
.io_type = SERIAL_IO_MEM }, \
- { .baud_base = EV96100_BASE_BAUD, .irq = EV96100INT_UART_0, \
+ { .baud_base = EV64120_BASE_BAUD, .irq = EV64120_UART_IRQ, \
.flags = STD_COM_FLAGS, \
- .iomem_base = EV96100_UART1_REGS_BASE, .iomem_reg_shift = 2, \
+ .iomem_base = EV64120_UART1_REGS_BASE, .iomem_reg_shift = 2, \
.io_type = SERIAL_IO_MEM },
#else
-#define EV96100_SERIAL_PORT_DEFNS
-#endif
-
-#ifdef CONFIG_MIPS_ITE8172
-#include <asm/it8172/it8172.h>
-#include <asm/it8172/it8172_int.h>
-#include <asm/it8712.h>
-#define ITE_SERIAL_PORT_DEFNS \
- { .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_UART_BASE), \
- .irq = IT8172_UART_IRQ, .flags = STD_COM_FLAGS, .port = PORT_16550 }, \
- { .baud_base = (24000000/(16*13)), .port = (IT8172_PCI_IO_BASE + IT8712_UART1_PORT), \
- .irq = IT8172_SERIRQ_4, .flags = STD_COM_FLAGS, .port = PORT_16550 }, \
- /* Smart Card Reader 0 */ \
- { .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_SCR0_BASE), \
- .irq = IT8172_SCR0_IRQ, .flags = STD_COM_FLAGS, .port = PORT_16550 }, \
- /* Smart Card Reader 1 */ \
- { .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_SCR1_BASE), \
- .irq = IT8172_SCR1_IRQ, .flags = STD_COM_FLAGS, .port = PORT_16550 },
-#else
-#define ITE_SERIAL_PORT_DEFNS
-#endif
-
-#ifdef CONFIG_MIPS_IVR
-#include <asm/it8172/it8172.h>
-#include <asm/it8172/it8172_int.h>
-#define IVR_SERIAL_PORT_DEFNS \
- { .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_UART_BASE), \
- .irq = IT8172_UART_IRQ, .flags = STD_COM_FLAGS, .port = PORT_16550 }, \
- /* Smart Card Reader 1 */ \
- { .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_SCR1_BASE), \
- .irq = IT8172_SCR1_IRQ, .flags = STD_COM_FLAGS, .port = PORT_16550 },
-#else
-#define IVR_SERIAL_PORT_DEFNS
+#define EV64120_SERIAL_PORT_DEFNS
#endif
#ifdef CONFIG_HAVE_STD_PC_SERIAL_PORT
@@ -239,10 +206,8 @@
#define SERIAL_PORT_DFNS \
DDB5477_SERIAL_PORT_DEFNS \
- EV96100_SERIAL_PORT_DEFNS \
+ EV64120_SERIAL_PORT_DEFNS \
IP32_SERIAL_PORT_DEFNS \
- ITE_SERIAL_PORT_DEFNS \
- IVR_SERIAL_PORT_DEFNS \
JAZZ_SERIAL_PORT_DEFNS \
STD_SERIAL_PORT_DEFNS \
MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS \
diff --git a/include/asm-mips/stacktrace.h b/include/asm-mips/stacktrace.h
new file mode 100644
index 0000000000000..07f873351a868
--- /dev/null
+++ b/include/asm-mips/stacktrace.h
@@ -0,0 +1,44 @@
+#ifndef _ASM_STACKTRACE_H
+#define _ASM_STACKTRACE_H
+
+#include <asm/ptrace.h>
+
+#ifdef CONFIG_KALLSYMS
+extern int raw_show_trace;
+extern unsigned long unwind_stack(struct task_struct *task, unsigned long *sp,
+ unsigned long pc, unsigned long *ra);
+#else
+#define raw_show_trace 1
+#define unwind_stack(task, sp, pc, ra) 0
+#endif
+
+static __always_inline void prepare_frametrace(struct pt_regs *regs)
+{
+#ifndef CONFIG_KALLSYMS
+ /*
+ * Remove any garbage that may be in regs (specially func
+ * addresses) to avoid show_raw_backtrace() to report them
+ */
+ memset(regs, 0, sizeof(*regs));
+#endif
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set noat\n\t"
+#ifdef CONFIG_64BIT
+ "1: dla $1, 1b\n\t"
+ "sd $1, %0\n\t"
+ "sd $29, %1\n\t"
+ "sd $31, %2\n\t"
+#else
+ "1: la $1, 1b\n\t"
+ "sw $1, %0\n\t"
+ "sw $29, %1\n\t"
+ "sw $31, %2\n\t"
+#endif
+ ".set pop\n\t"
+ : "=m" (regs->cp0_epc),
+ "=m" (regs->regs[29]), "=m" (regs->regs[31])
+ : : "memory");
+}
+
+#endif /* _ASM_STACKTRACE_H */
diff --git a/include/asm-mips/tx4938/tx4938_mips.h b/include/asm-mips/tx4938/tx4938_mips.h
index cf89b205f1039..5f8498fef0056 100644
--- a/include/asm-mips/tx4938/tx4938_mips.h
+++ b/include/asm-mips/tx4938/tx4938_mips.h
@@ -1,5 +1,5 @@
/*
- * linux/include/asm-mips/tx4938/tx4938_bitmask.h
+ * linux/include/asm-mips/tx4938/tx4938_mips.h
* Generic bitmask definitions
*
* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
diff --git a/include/asm-mips/unistd.h b/include/asm-mips/unistd.h
index c39142920fe6e..685c91467e634 100644
--- a/include/asm-mips/unistd.h
+++ b/include/asm-mips/unistd.h
@@ -1212,45 +1212,6 @@ type name (atype a,btype b,ctype c,dtype d,etype e,ftype f) \
# define __ARCH_WANT_COMPAT_SYS_TIME
# endif
-#ifdef __KERNEL_SYSCALLS__
-
-#include <linux/compiler.h>
-#include <linux/types.h>
-#include <linux/linkage.h>
-#include <asm/ptrace.h>
-#include <asm/sim.h>
-
-/*
- * we need this inline - forking from kernel space will result
- * in NO COPY ON WRITE (!!!), until an execve is executed. This
- * is no problem, but for the stack. This is handled by not letting
- * main() use the stack at all after fork(). Thus, no function
- * calls - which means inline code for fork too, as otherwise we
- * would use the stack upon exit from 'fork()'.
- *
- * Actually only pause and fork are needed inline, so that there
- * won't be any messing with the stack from main(), but we define
- * some others too.
- */
-static inline _syscall3(int,execve,const char *,file,char **,argv,char **,envp)
-
-asmlinkage unsigned long sys_mmap(
- unsigned long addr, size_t len,
- int prot, int flags,
- int fd, off_t offset);
-asmlinkage long sys_mmap2(
- unsigned long addr, unsigned long len,
- unsigned long prot, unsigned long flags,
- unsigned long fd, unsigned long pgoff);
-asmlinkage int sys_execve(nabi_no_regargs struct pt_regs regs);
-asmlinkage int sys_pipe(nabi_no_regargs struct pt_regs regs);
-struct sigaction;
-asmlinkage long sys_rt_sigaction(int sig,
- const struct sigaction __user *act,
- struct sigaction __user *oact,
- size_t sigsetsize);
-
-#endif /* __KERNEL_SYSCALLS__ */
#endif /* !__ASSEMBLY__ */
/*
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-05-26 19:27:15 +0000