6c7f4f1e51c2 ("cxl/core/regs: Make cxl_map_{component, device}_regs() device generic")
43a2fb3aef16 ("cxl/pci: Kill cxl_map_regs()")
1191ca102d32 ("cxl/pci: Cleanup cxl_map_device_regs()")
2703c16c75ae ("cxl/core/port: Add switch port enumeration")
4112a08dd3c5 ("cxl/pci: Store component register base in cxlds")
664bf115833c ("cxl/core/port: Remove @host argument for dport + decoder enumeration")
54cdbf845cf7 ("cxl/port: Add a driver for 'struct cxl_port' objects")
83fbdbe4c186 ("cxl/core: Emit modalias for CXL devices")
d17d0540a0db ("cxl/core/hdm: Add CXL standard decoder enumeration to the core")
98d2d3a26454 ("cxl/core: Generalize dport enumeration in the core")
af9cae9facc2 ("cxl/pci: Rename pci.h to cxlpci.h")
c978f1b10aba ("cxl/port: Up-level cxl_add_dport() locking requirements to the caller")
a46cfc0f011c ("cxl/pmem: Introduce a find_cxl_root() helper")
5ff7316f6fea ("cxl/port: Introduce cxl_port_to_pci_bus()")
3c5b90395525 ("cxl: Prove CXL locking")
53fa1bff3426 ("cxl/core: Track port depth")
d2b61ed2ff63 ("cxl/core/port: Make passthrough decoder init implicit")
d54c1bbe2d34 ("cxl/core/port: Clarify decoder creation")
608135db1b79 ("cxl/core: Convert decoder range to resource")
303ebc1b1741 ("cxl/acpi: Map component registers for Root Ports")