6b07b6d2bd66 ("drm/i915: Use wait_for_atomic_us when waiting for gt fifo")
2d1fe0734087 ("drm/i915: Do not use {HAS_*, IS_*, INTEL_INFO}(dev_priv->dev)")
b4ac5afc6b83 ("drm/i915: replace for_each_engine()")
c3232b1883e0 ("drm/i915: introduce for_each_engine_id()")
ee4b6faf96a9 ("drm/i915: Modify reset func to handle per engine resets")
117897f42c87 ("drm/i915: More renaming of rings to engines")
666796da7abb ("drm/i915: More intel_engine_cs renaming")
4a570db57c05 ("drm/i915: Rename intel_engine_cs struct members")
0bc40be85f33 ("drm/i915: Rename intel_engine_cs function parameters")
e2f80391478a ("drm/i915: Rename local struct intel_engine_cs variables")
8106ddbd7733 ("drm/i915: Store a direct pointer to shared dpll in intel_crtc_state")
7abd4b35a577 ("drm/i915: Move shared dpll code to a new file")
24a65e624bcd ("drm/i915/hangcheck: Prevent long walks across full-ppgtt")
d431440cce24 ("drm/i915: Generalise common GPU engine reset request/unrequest code")
8de1b23efaed ("drm/i915/lrc: Do not wait atomically when stopping engines")
f85db0590dd8 ("drm/i915/error: Capture WA ctx batch in error state")
c6a2ac712d7d ("drm/i915: Execlists small cleanups and micro-optimisations")
99cf8ea16595 ("drm/i915/lrc: Only set RS ctx enable in ctx control reg if there is a RS")
715629190ef3 ("drm/i915/gen9: Set value of Indirect Context Offset based on gen version")
12fda3876d08 ("drm/i915/ibx: Ensure the HW is powered during PLL HW readout")
3f441b825d92 ("drm/i915: Use appropriate spinlock flavour")
fb1a38a92ba8 ("drm/i915: Clear shared dpll based on old state, v2.")
f4e2deceb6aa ("drm/i915: Fix premature LRC unpin in GuC mode")
a0b4a6a8dbb1 ("drm/i915: Extract context unpinning to its own function")
e5292823c142 ("drm/i915: Make LRC (un)pinning work on context and engine")
6107497eee9f ("drm/i915/skl: Add GEN8_L3SQCREG4 to HW whitelist")
a786d53a2cf1 ("drm/i915/bxt: Add GEN8_L3SQCREG4 to HW whitelist")
2c8580e4e21c ("drm/i915/bxt: Add GEN9_CS_DEBUG_MODE1 to HW whitelist")
3669ab6191b2 ("drm/i915/gen9: Add HDC_CHICKEN1 to HW whitelist")
e0f3fa096d6f ("drm/i915/gen9: Add GEN8_CS_CHICKEN1 to HW whitelist")
33136b06d549 ("drm/i915/gen9: Add framework to whitelist specific GPU registers")
397097b02619 ("drm/i915/guc: Decouple GuC engine id from ring id")
77b04a0428ea ("drm/i915: More use of the cached LRC state")
426960bed321 ("drm/i915: Seal busy-ioctl uABI and prevent leaking of internal ids")
de1add360522 ("drm/i915: Decouple execbuf uAPI from internal implementation")
7c17d377374d ("drm/i915: Use ordered seqno write interrupt generation on gen8+ execlists")
e28e404c3e93 ("drm/i915: tidy up a few leftovers")
ed54c1a1d11c ("drm/i915: abolish separate per-ring default_context pointers")
268270883921 ("drm/i915: simplify allocation of driver-internal requests")
82352e908acd ("drm/i915: Cache LRC state page in the context")
0eb973d31d0a ("drm/i915: Cache ringbuffer GTT VMA")
ca82580c9cea ("drm/i915: Do not call API requiring struct_mutex where it is not available")
2da80b57c69a ("Merge remote-tracking branch 'airlied/drm-next' into drm-intel-next-queued")