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| author | Lubomir Rintel <lkundrak@v3.sk> | 2020-04-13 07:55:08 +0200 |
|---|---|---|
| committer | Lubomir Rintel <lkundrak@v3.sk> | 2020-08-14 01:52:18 +0200 |
| commit | 001846728ce417f5d7ce0aab66d7efaaf01e986b (patch) | |
| tree | 358d54cd9dca66da0685f21e293a01a354ee2ba9 | |
| parent | 8576baaac2020d195dcc41669ab5f744b950d4e3 (diff) | |
| download | openfirmware-001846728ce417f5d7ce0aab66d7efaaf01e986b.tar.gz | |
mmp2/clk: increase MPMU reg range
The ACGR is at the offset of 0x1024, beyond the 4k initially assigned to
the MPMU range.
| -rw-r--r-- | cpu/arm/mmp2/clk.fth | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/cpu/arm/mmp2/clk.fth b/cpu/arm/mmp2/clk.fth index a8a88ed0..e8d623db 100644 --- a/cpu/arm/mmp2/clk.fth +++ b/cpu/arm/mmp2/clk.fth @@ -54,7 +54,7 @@ d# 10001 constant mmp2-vmeta-clk# " marvell,mmp3-clock" +compatible [then] -h# d405.0000 encode-int h# 1000 encode-int encode+ +h# d405.0000 encode-int h# 2000 encode-int encode+ h# d428.2800 encode-int encode+ h# 400 encode-int encode+ h# d401.5000 encode-int encode+ h# 1000 encode-int encode+ " reg" property |