I'm actually surprised this time. There aren't any new Qualcomm SoC clk

drivers. And there's zero diff in the core clk framework. Instead we have new
clk drivers for STM and Sophgo, with Samsung^WGoogle in third for the diffstat
because they introduced HSI0 and HSI2 clk drivers for Google's GS101 SoC (high
speed interface things like PCIe, UFS, and MMC). Beyond those big diffs there's
the usual updates to various clk drivers for incorrect parent descriptions or
mising MODULE_DEVICE_TABLE()s, etc. Nothing in particular stands out as super
interesting here.

New Drivers:
 - STM32MP257 SoC clk driver
 - Airoha EN7581 SoC clk driver
 - Sophgo CV1800B, CV1812H and SG2000 SoC clk driver
 - Loongson-2k0500 and Loongson-2k2000 SoC clk driver
 - Add HSI0 and HSI2 clock controllers for Google GS101
 - Add i.MX95 BLK CTL clock driver

Updates:
 - Allocate clk_ops dynamically for SCMI clk driver
 - Add support in qcom RCG and RCG2 for multiple configurations for the same frequency
 - Use above support for IPQ8074 NSS port 5 and 6 clocks to resolve issues
 - Fix the Qualcomm APSS IPQ5018 PLL to fix boot failures of some boards
 - Cleanups and fixes for Qualcomm Stromer PLLs
 - Reduce max CPU frequency on Qualcomm APSS IPQ5018
 - Fix Kconfig dependencies of Qualcomm SM8650 GPU and SC8280XP camera
   clk drivers
 - Make Qualcomm MSM8998 Venus clocks functional
 - Cleanup downstream remnants related to DisplayPort across Qualcomm
   SM8450, SM6350, SM8550, and SM8650
 - Reuse the Huayra APSS register map on Qualcomm MSM8996 CBF PLL
 - Use a specific Qualcomm QCS404 compatible for the otherwise generic
   HFPLL
 - Remove Qualcomm SM8150 CPUSS AHB clk as it is unused
 - Remove an unused field in the Qualcomm RPM clk driver
 - Add missing MODULE_DEVICE_TABLE to Qualcomm MSM8917 and MSM8953
   global clock controller drivers
 - Allow choice of manual or firmware-driven control over PLLs, needed
   to fully implement CPU clock controllers on Exynos850
 - Correct PLL clock IDs on ExynosAutov9
 - Propagate certain clock rates to allow setting proper SPI clock
   rates on Google GS101
 - Mark certain Google GS101 clocks critical
 - Convert old S3C64xx clock controller bindings to DT schema
 - Add new PLL rate and missing mux on Rockchip rk3568
 - Add missing reset line on Rockchip rk3588
 - Removal of an unused field in struct rockchip_mmc_clock
 - Amlogic s4/a1: add regmap maximum register for proper debugfs dump
 - Amlogic s4: add MODULE_DEVICE_TABLE() on pll and periph controllers
 - Amlogic pll driver: print clock name on lock error to help debug
 - Amlogic vclk: finish dsi clock path support
 - Amlogic license: fix occurence "GPL v2" as reported by checkpatch
 - Add PM runtime support to i.MX8MP Audiomix
 - Add DT schema for i.MX95 Display Master Block Control
 - Convert to platform remove callback returning void for i.MX8MP
   Audiomix
 - Add SPI (MSIOF) and external interrupt (INTC-EX) clocks on Renesas R-Car V4M
 - Add interrupt controller (PLIC) clock and reset on Renesas RZ/Five
 - Prepare power domain support for Renesas RZ/G2L family members, and add
   actual support on Renesas RZ/G3S SoC
 - Add thermal, serial (SCIF), and timer (CMT/TMU) clocks on Renesas R-Car V4M
 - Add additional constraints to Allwinner A64 PLL MIPI clock
 - Fix autoloading sunxi-ng clocks when build as a module
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