arch/mips/Kconfig v2.6.32-rc8

CAVIUM_OCTEON_2ND_KERNEL

Build the kernel to be used as a 2nd kernel on the same chip

This option configures this kernel to be linked at a different
address and use the 2nd uart for output. This allows a kernel built
with this option to be run at the same time as one built without this
option.

CAVIUM_OCTEON_HW_FIX_UNALIGNED

Enable hardware fixups of unaligned loads and stores

Configure the Octeon hardware to automatically fix unaligned loads
and stores. Normally unaligned accesses are fixed using a kernel
exception handler. This option enables the hardware automatic fixups,
which requires only an extra 3 cycles. Disable this option if you
are running code that relies on address exceptions on unaligned
accesses.

CAVIUM_OCTEON_CVMSEG_SIZE

Number of L1 cache lines reserved for CVMSEG memory

CVMSEG LM is a segment that accesses portions of the dcache as a
local memory; the larger CVMSEG is, the smaller the cache is.
This selects the size of CVMSEG LM, which is in cache blocks. The
legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is
between zero and 6192 bytes).

CAVIUM_OCTEON_LOCK_L2

Lock often used kernel code in the L2

Enable locking parts of the kernel into the L2 cache.

CAVIUM_OCTEON_LOCK_L2_TLB

Lock the TLB handler in L2

Lock the low level TLB fast path into L2.

CAVIUM_OCTEON_LOCK_L2_EXCEPTION

Lock the exception handler in L2

Lock the low level exception handler into L2.

CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT

Lock the interrupt handler in L2

Lock the low level interrupt handler into L2.

CAVIUM_OCTEON_LOCK_L2_INTERRUPT

Lock the 2nd level interrupt handler in L2

Lock the 2nd level interrupt handler in L2.

CAVIUM_OCTEON_LOCK_L2_MEMCPY

Lock memcpy() in L2

Lock the kernel's implementation of memcpy() into L2.