AVR32 is a high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption and high code density. There is an AVR32 Linux project with a web page at http://avr32linux.org/.
The Hammerhead platform is built around an AVR32 32-bit microcontroller from Atmel. It offers versatile peripherals, such as ethernet, usb device, usb host etc. The board also incorporates a power supply and is a Power over Ethernet (PoE) Powered Device (PD). Additionally, a Cyclone III FPGA from Altera is integrated on the board. The FPGA is mapped into the 32-bit AVR memory bus. The FPGA offers two DDR2 SDRAM interfaces, which will cover even the most exceptional need of memory bandwidth. Together with the onboard video decoder the board is ready for video processing. For more information see: http://www.miromico.com/hammerhead
Merisc is the family name for a range of AVR32-based boards. The boards are designed to be used in a man-machine interfacing environment, utilizing a touch-based graphical user interface. They host a vast range of I/O peripherals as well as a large SDRAM & Flash memory bank. For more information see: http://www.martinsson.se/merisc
Say Y to generate an Ownership Trace message on every context switch, enabling Nexus-compliant debuggers to keep track of the PID of the currently executing task.
Say Y here and pass the nmi_debug command-line parameter to the kernel to turn on NMI debugging. Depending on the value of the nmi_debug option, various pieces of information will be dumped to the console when a Non-Maskable Interrupt happens.
If you don't have a boot loader capable of passing a command line string to the kernel, you may specify one here. As a minimum, you should specify the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
This enables the CPU frequency driver for AT32AP processors. For details, take a look in <file:Documentation/cpu-freq>. If in doubt, say N.